Abstract: While a storage region 15 has of many dispersed particulates (dots) (15a), the surface density of the particulates (15a) is set to be higher than that of structural holes (pin holes) produced in a tunnel insulating film (14a), or the number of the particulates (15a) in the storage region (15) is set to five or more. While a conduction region (13c) is formed by a polysilicon layer (13) having a surface roughness of 0.1 nm to 100 nm, the number of the particulates (15a) in the storage region (15) is set to be larger than the number of crystal grains in the conduction region (13c). Even when a defect such as a pin hole occurs in the tunnel insulating film (14a) and charges stored in a part of the particulates are leaked, the charges stored in the particulates formed in a region where no defect occurs are not leaked. Thus, information can be held for a long time.

Abstract: A memory device, a manufacturing method thereof, and an integrated circuit thereof are provided for storing information over a long period of time even if the memory device is manufactured at low temperatures. On a substrate made of glass, etc., a memory transistor and a selection transistor are formed, with a silicon nitride film and a silicon dioxide film in between. The memory transistor and the selection transistor are connected in series at a second impurity region. The conduction region for memory of the memory transistor is made of non-single crystal silicon and a storage region comprises a plurality of dispersed particulates made of non-single crystal silicon. Therefore, electrical charges can be stored partially if a tunnel insulating film has any defects. The tunnel insulating film is formed by exposing the surface of the conduction region for memory to the ionized gas containing oxygen atoms.

Abstract: It is made possible to conduct writing and erasing information at high speed and with a low gate voltage, attain high integration with reduced power dissipation, and retain information accurately. It is also made possible to change the conductivity of a conduction layer efficiently depending on whether there are accumulated charges or not, even if the device is made finer. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. In the conduction layer, one insulation portion and one insulation portion allowing charge tunneling are formed with the barrier layer in between. The capacitance of the insulation portions is made smaller than e.sup.2 /k.sub.B T (where e is the electric prime quantity, k.sub.B is the Boltzmann's constant, and T is operation temperature).

Abstract: A quantum device functioning as a memory device is provided for allowing high-speed writing and erasing of data with a low gate voltage. A source electrode and a drain electrode are formed on a substrate. A gate electrode is formed between the source and drain electrodes. Between the substrate and the gate electrode, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer and a third barrier layer are stacked to form coupled quantum well layer. The thickness of each of the first and second barrier layers allows electron tunneling. The thickness of the third barrier layer does not allow electron tunneling. The energy level of the first quantum well layer is higher than the Fermi level of a conduction layer. The energy level of the second quantum well layer is lower than the energy level of the first quantum well layer.

Abstract: A method of manufacturing a quantum device such as a coupled quantum boxes device are disclosed. The quantum device comprises: a semiconductor substrate; a plurality of box portions made of a first semiconductor; and a layer made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions of a first semiconductor on a semiconductor substrate; and covering circumferences of the box portions with a layer of a second semiconductor, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.

Abstract: A quantum box array comprising a plurality of quantum boxes is made by providing a plurality of box-shaped quantum well portions on a first barrier layer and a second barrier layer covering the quantum well portions. The quantum box array is designed so that interaction energy between electrons or holes is amply larger than transfer energy between the quantum boxes. A control electrode is provided on the second barrier layer to vary the number of electrons or holes in the quantum box array by changing the potential of the control electrode. In spite of using a relatively small number of electrons or holes, the quantum device can suppress fluctuation in density of electrons or holes, can have three or more states, and reduces the power consumption.

Abstract: A quantum operational device includes a plurality of quantum boxes arranged in a plurality of stages isolated by a distance which permits tunnelling of electrons or holes through the distance, uses as bit information the presence or absence of an electron or a hole in each of the quantum boxes, and prohibits tunnelling of an electron or a hole from a quantum box in a stage to another quantum box in an adjacent stage when an electron or a hole exists in the quantum box in the adjacent stage. The device only needs quite low power, performs operation at a high speed, and can be fabricated by a simple manufacturing process.