Patents by Inventor Kazunari Suzuki

Kazunari Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8448655
    Abstract: An ultrasonic cleaning device is provided which can easily cope with an increase in a diameter of a cleaning surface of an object to be cleaned. An ultrasonic cleaning device according to the present invention includes an ultrasonic transducer 13 for providing ultrasonic energy to a propagation liquid 15, an ultrasonic propagation tube 12 for flowing the propagation liquid provided with the ultrasonic energy by the ultrasonic transducer, a holding mechanism disposed below the ultrasonic propagation tube for holding an object to be cleaned 21, and a cleaning liquid supply mechanism for supplying a cleaning liquid to a cleaning surface of the object to be cleaned held by the holding mechanism, and the ultrasonic propagation tube 12 is disposed so that a side surface thereof may contact a liquid film 19 of the cleaning liquid formed on the cleaning surface by supplying the cleaning liquid to the cleaning surface by the cleaning liquid supply mechanism.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: May 28, 2013
    Assignee: Kaijo Corporation
    Inventors: Kazunari Suzuki, Ki Han
  • Patent number: 8378459
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Toshihide Uematsu, Chuichi Miyazaki, Kazunari Suzuki, Yasuyuki Nakajima, Yoshiyuki Abe, Kenji Kohzu, Kosuke Kitaichi, Shinya Ogane
  • Patent number: 8300822
    Abstract: A system for processing a communication data item. The communication data item is divided into at least two unencrypted packets to be encrypted. Each encrypted packet is generated from a corresponding unencrypted packet. Each unencrypted packet has a packet header and plaintext data. The packet header has an identifier field that includes a packet identifier that is identical for all unencrypted packets. Generating an encrypted packet for each unencrypted packet includes: determining a vector identifier from the identical packet identifier, wherein the vector identifier is associated with the identical packet identifier; ascertaining an initial vector from the vector identifier; and forming an encrypted packet header by inserting the vector identifier into a first portion of the packet header and encrypting a second portion of the packet header through use of the initial vector. The encrypted packets are subsequently decrypted and combined to reconstruct the communication data item.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Shinji Nakai, Masakazu Satoh, Kazunari Suzuki
  • Publication number: 20120257507
    Abstract: A system and method of transmitting data across a first link aggregation formed by an intermediate switch and a downstream switch, the intermediate switch adopting a Media-Access Card (MAC)-address-based load sharing algorithm for distributing traffic among links to the downstream switch interfaced with a final destination device. The method comprises: receiving a packet having a MAC header and an IP header at an input port of an upstream switch for transmission from the upstream switch to the intermediate switch, the upstream switch and intermediate switch forming a second link aggregation; re-writing, at the upstream switch, the source MAC address of the received packet to a different source address; sending the packet through the second link aggregation to the intermediate switch, the intermediate switch implementing the load sharing algorithm for sending the packet to the downstream switch along a link through the first link aggregation to the destination device.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Masakazu Sato, Satoshi Nakajima, Kazunari Suzuki
  • Patent number: 8274980
    Abstract: A system and method of transmitting data across a link aggregation group, the method comprises: receiving a packet sourced from a client having a MAC header and an IP header at an input port of a first upstream switch for transmission from the first upstream switch along a link aggregation and at least two down stream switches to a server, said MAC header having a Destination MAC address and a Source MAC address, and the IP header having a Source IP address and a Destination IP address; changing the destination MAC address from a down stream destination to another down stream destination; sending the packet through a first link aggregation to a first down stream switch; using a hash calculation for changing the Source MAC address of the packet in the first down stream switch to a new address; sending the packet through a second link aggregation to a second down stream switch having an address; and sending the packet from the second down stream switch to a server having a server address.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Masakazu Sato, Satoshi Nakajima, Kazunari Suzuki
  • Patent number: 8156646
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: April 17, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Publication number: 20110145573
    Abstract: A system for processing a communication data item. The communication data item is divided into at least two unencrypted packets to be encrypted. Each encrypted packet is generated from a corresponding unencrypted packet. Each unencrypted packet has a packet header and plaintext data. The packet header has an identifier field that includes a packet identifier that is identical for all unencrypted packets. Generating an encrypted packet for each unencrypted packet includes: determining a vector identifier from the identical packet identifier, wherein the vector identifier is associated with the identical packet identifier; ascertaining an initial vector from the vector identifier; and forming an encrypted packet header by inserting the vector identifier into a first portion of the packet header and encrypting a second portion of the packet header through use of the initial vector. The encrypted packets are subsequently decrypted and combined to reconstruct the communication data item.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shinji Nakai, Masakazu Satoh, Kazunari Suzuki
  • Patent number: 7943861
    Abstract: A composite layer composed of an Ni layer 72 and a Pd layer 73 is formed on a solder pad 77U, and a solder 76? on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by means of thermal stress.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 17, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 7869597
    Abstract: A method for processing a communication data item. The communication data item is divided into at least two unencrypted packets to be encrypted. Each encrypted packet is generated from a corresponding unencrypted packet. Each unencrypted packet has a packet header and plaintext data. The packet header has an identifier field that includes a packet identifier. The packet identifier is identical for all unencrypted packets. Generating an encrypted packet for each unencrypted packet includes: determining a vector identifier from the identical packet identifier, wherein the vector identifier is associated with the identical packet identifier; ascertaining an initial vector from the vector identifier; and forming an encrypted packet header by inserting the vector identifier into a first portion of the packet header and encrypting a second portion of the packet header through use of the initial vector. The encrypted packets are subsequently decrypted and combined to reconstruct the communication data item.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Shinji Nakai, Masakazu Satoh, Kazunari Suzuki
  • Patent number: 7869358
    Abstract: A communication relay apparatus, information management system, and control method and program therefor. The communication relay apparatus includes several communication ports, and that includes a communication relay section, a buffer, a control signal transmitting section, a bandwidth information acquiring section, and a transmission interval control section.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Masakazu Satoh, Kazunari Suzuki
  • Publication number: 20100308442
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro NAKA, Naotaka TANAKA, Toshihide UEMATSU, Chuichi MIYAZAKI, Kazunari SUZUKI, Yasuyuki NAKAJIMA, Yoshiyuki ABE, Kenji KOHZU, Kosuke KITAICHI, Shinya OGANE
  • Publication number: 20100215042
    Abstract: A system and method of transmitting data across a link aggregation group, the method comprises: receiving a packet sourced from a client having a MAC header and an IP header at an input port of a first upstream switch for transmission from the first upstream switch along a link aggregation and at least two down stream switches to a server, said MAC header having a Destination MAC address and a Source MAC address, and the IP header having a Source IP address and a Destination IP address; changing the destination MAC address from a down stream destination to another down stream destination; sending the packet through a first link aggregation to a first down stream switch; using a hash calculation for changing the Source MAC address of the packet in the first down stream switch to a new address; sending the packet through a second link aggregation to a second down stream switch having an address; and sending the packet from the second down stream switch to a server having a server address.
    Type: Application
    Filed: February 26, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Masakazu Sato, Satoshi Nakajima, Kazunari Suzuki
  • Patent number: 7759224
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20100163083
    Abstract: An ultrasonic cleaning device is provided which can easily cope with an increase in a diameter of a cleaning surface of an object to be cleaned. An ultrasonic cleaning device according to the present invention includes an ultrasonic transducer 13 for providing ultrasonic energy to a propagation liquid 15, an ultrasonic propagation tube 12 for flowing the propagation liquid provided with the ultrasonic energy by the ultrasonic transducer, a holding mechanism disposed below the ultrasonic propagation tube for holding an object to be cleaned 21, and a cleaning liquid supply mechanism for supplying a cleaning liquid to a cleaning surface of the object to be cleaned held by the holding mechanism, and the ultrasonic propagation tube 12 is disposed so that a side surface thereof may contact a liquid film 19 of the cleaning liquid formed on the cleaning surface by supplying the cleaning liquid to the cleaning surface by the cleaning liquid supply mechanism.
    Type: Application
    Filed: August 19, 2009
    Publication date: July 1, 2010
    Inventors: Kazunari Suzuki, Ki Han
  • Patent number: 7678706
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: March 16, 2010
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 7647420
    Abstract: A method and apparatus for controlling a transmission of data from a first storage device to a second storage device. The first storage device includes a recording unit for recording the data, a buffer for temporarily storing the data read from the recording unit, and a transmission unit for transmitting the data read from the buffer. It is determined that sufficient buffer space in the buffer is not available for the transmission of the data in a predetermined time interval. It is ascertained whether a transmission error exists in a communication line connecting the first storage device to the second storage device. If the transmission error exits, then the transmission unit is controlled to not perform the transmission of the data from the first storage device; otherwise the transmission unit is not controlled to not perform the transmission of the data from the first storage device.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Masakazu Satoh, Kazunari Suzuki
  • Publication number: 20090285980
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Application
    Filed: June 30, 2009
    Publication date: November 19, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Tsutomu IWAI, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 7605682
    Abstract: In a magnetic core type laminated inductor, magnetic gap layers are interposed between layers of conductive patterns, and the magnetic gap layers are formed separately on multiple layers mutually distant from each other while sandwiching a magnetic body layer. Moreover, the multiple magnetic gap layers are vertically symmetrically disposed relative to a central portion of lamination in a magnetically equivalent fashion, and the respective magnetic gap layers interpose at least two layers of the conductive patterns therebetween.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: October 20, 2009
    Assignee: FDK Corporation
    Inventors: Fumiaki Nakao, Kazunari Suzuki, Mikio Kitaoka, Daisuke Matsubayashi, Shigenori Suzuki
  • Patent number: 7541667
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: June 2, 2009
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Patent number: RE43443
    Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 5, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai