Patents by Inventor Kazunari Suzuki

Kazunari Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528014
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: May 5, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Patent number: 7466649
    Abstract: In one general embodiment, a method for setting a value of waiting time for switching is provided. At a node in a sonet ring, it is determined which path to the node is an actual path and which path is a preliminary path. Additionally, it is determined whether a one way fiber transmission delay of the actual path is less than a one way fiber transmission delay of the preliminary path. If the one way fiber transmission delay of the actual path is greater than the one way fiber transmission delay of the preliminary path, a switching time is set to zero and normal switching is performed. If the one way fiber transmission delay of the actual path is less than the one way fiber transmission delay of the preliminary path, a switching time is set equal to the one way fiber transmission delay of the preliminary path minus the one way fiber transmission delay of the actual path and it is determined whether a path alarm indication signal (AIS) occurred in the actual path.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Chienho Chen, Masakazu Satoh, Kazunari Suzuki, Takashi Murata
  • Publication number: 20080286948
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 20, 2008
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 7452787
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20080264681
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Application
    Filed: March 15, 2005
    Publication date: October 30, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 7422024
    Abstract: An ultrasonic shower cleaning apparatus is disclosed which is capable of efficiently cleaning both surfaces of an article and configured to have a reduced size enabling an installation space thereof to be decreased. A pair of ultrasonic shower cleaning mechanisms each include a nozzle, a disc-shaped ultrasonic transducer arranged so as to face a backward end of the nozzle and an inlet port for a cleaning liquid formed opposite to a side surface of the nozzle. The ultrasonic shower cleaning mechanisms are integrally incorporated in one casing in such a manner that axes of the nozzles cross each other at a predetermined angle. The casing is provided with one inlet branch port connected to the inlet ports of the ultrasonic shower cleaning mechanisms. The casing may have a groove formed therein in which an edge of the article arranged between the two nozzles can be inserted.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: September 9, 2008
    Assignee: Kaijo Corporation
    Inventors: Seigo Takahashi, Junpei Ohkawara, Kazunari Suzuki
  • Patent number: 7323788
    Abstract: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Kazunari Suzuki, Hirohito Ohashi
  • Publication number: 20070298545
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Application
    Filed: July 20, 2007
    Publication date: December 27, 2007
    Inventors: Yoshinori MIYAKI, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20070170601
    Abstract: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.
    Type: Application
    Filed: March 29, 2007
    Publication date: July 26, 2007
    Inventors: Yoshinori Miyaki, Kazunari Suzuki, Hirohito Ohashi
  • Patent number: 7247576
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 24, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20070116285
    Abstract: A method for processing a communication data item. The communication data item is divided into at least two unencrypted packets to be encrypted. Each encrypted packet is generated from a corresponding unencrypted packet. Each unencrypted packet has a packet header and plaintext data. The packet header has an identifier field that includes a packet identifier. The packet identifier is identical for all unencrypted packets. Generating an encrypted packet for each unencrypted packet includes: determining a vector identifier from the identical packet identifier, wherein the vector identifier is associated with the identical packet identifier; ascertaining an initial vector from the vector identifier; and forming an encrypted packet header by inserting the vector identifier into a first portion of the packet header and encrypting a second portion of the packet header through use of the initial vector. The encrypted packets are subsequently decrypted and combined to reconstruct the communication data item.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 24, 2007
    Applicant: International Business Machines Corporation
    Inventors: Shinji Nakai, Masakazu Satoh, Kazunari Suzuki
  • Patent number: 7211903
    Abstract: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: May 1, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Kazunari Suzuki, Hirohito Ohashi
  • Patent number: 7199469
    Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 3, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
  • Patent number: 7176060
    Abstract: A multi-function structure of a plug-in universal IC card is to be promoted and the manufacturing cost is to be reduced. The body of the plug-in UICC is constructed of a molding resin. A tape substrate and a chip mounted on one side of the tape substrate are sealed in the interior of the molding resin. A side opposite to the chip mounting side of the tape substrate is exposed to the exterior of the molding resin and constitutes a surface portion of the plug-in UICC. Contact patterns serving as external terminals of the plug-in UICC are formed on the surface of the tape substrate exposed to the exterior of the molding resin. In the plug-in UICC whose body is constructed of molding resin, cracking of the chip can be prevented effectively even in the case where the chip is large-sized.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Nobuaki Yamada, Kazunari Suzuki, Bunshi Kuratomi, Hiroaki Tanaka, Akira Onozawa
  • Patent number: 7148081
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked on a mounting substrate, an adhesive material formed of resin mainly having a thermosetting property is applied to a semiconductor chip mounting region on the mounting substrate. After mounting semiconductor chips on the adhesive material, the adhesive material is cured by heat treatment. When these parts are naturally cooled to a normal temperature, the mounting substrate warps in a convex shape due to the difference in an ? value between the mounting substrate and the semiconductor chip. However, pads are connected by wire bonding and, an adhesive material formed of resin having a thermoplastic property is laminated to the semiconductor chip. Then, a spacer chip is bonded to the adhesive material by thermal compression bonding. Accordingly, due to heat generated at the time of thermal compression bonding, the mounting substrate and the semiconductor chip become substantially flat.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: December 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tomoko Higashino, Kazunari Suzuki, Chuichi Miyazaki
  • Publication number: 20060212603
    Abstract: A method and apparatus for controlling a transmission of data from a first storage device to a second storage device. The first storage device includes a recording unit for recording the data, a buffer for temporarily storing the data read from the recording unit, and a transmission unit for transmitting the data read from the buffer. It is determined that sufficient buffer space in the buffer is not available for the transmission of the data in a predetermined time interval. It is ascertained whether a transmission error exists in a communication line connecting the first storage device to the second storage device. If the transmission error exits, then the transmission unit is controlled to not perform the transmission of the data from the first storage device; otherwise the transmission unit is not controlled to not perform the transmission of the data from the first storage device.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 21, 2006
    Applicant: International Business Machines Corporation
    Inventors: Masakazu Satoh, Kazunari Suzuki
  • Publication number: 20060209893
    Abstract: A communication relay apparatus, information management system, and control method and program therefor. The communication relay apparatus includes several communication ports, and that includes a communication relay section, a buffer, a control signal transmitting section, a bandwidth information acquiring section, and a transmission interval control section.
    Type: Application
    Filed: March 14, 2006
    Publication date: September 21, 2006
    Applicant: International Business Machines Corporation
    Inventors: Masakazu Satoh, Kazunari Suzuki
  • Publication number: 20060152325
    Abstract: In a magnetic core type laminated inductor, magnetic gap layers are interposed between layers of conductive patterns, and the magnetic gap layers are formed separately on multiple layers mutually distant from each other while sandwiching a magnetic body layer. Moreover, the multiple magnetic gap layers are vertically symmetrically disposed relative to a central portion of lamination in a magnetically equivalent fashion, and the respective magnetic gap layers interpose at least two layers of the conductive patterns therebetween.
    Type: Application
    Filed: January 24, 2006
    Publication date: July 13, 2006
    Applicant: FDK Corporation
    Inventors: Fumiaki Nakao, Kazunari Suzuki, Mikio Kitaoka, Daisuke Matsubayashi, Shigenori Suzuki
  • Patent number: 7074844
    Abstract: An adhesive, comprising (A) a polymeric MDI, (B) modified polyvinyl acetate emulsion, (C) aqueous polyvinyl alcohol solution, and (D) a filler. Preferably, a mass ratio of A:B:C:D is 30:(60–160):(50–160):(10–140) provided that the aqueous polyvinyl alcohol solution (C) is in a concentration of 10% by mass.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: July 11, 2006
    Assignee: Yamaha Corporation
    Inventors: Ritsuo Iwata, Hironao Nagashima, Tomohide Ogata, Kazunari Suzuki, Koji Nakajima
  • Patent number: 7015069
    Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: March 21, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa