Patents by Inventor Kazushige Kawasaki
Kazushige Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099013Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
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Patent number: 11871576Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: GrantFiled: December 7, 2020Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
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Publication number: 20230282536Abstract: According to one embodiment, a semiconductor device includes a wiring substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. A first electrode is on the first surface. A semiconductor element is on the wiring substrate and electrically connected to the first electrode. A resin layer covers the semiconductor element and the first surface from a first direction orthogonal to the first surface. A portion of the resin layer contacts the side surface of the wiring substrate from a second direction parallel to the first surface. The resin layer has an outside side surface that is substantially parallel to the first direction.Type: ApplicationFiled: August 26, 2022Publication date: September 7, 2023Inventors: Kazushige Kawasaki, Satoru Itakura
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Publication number: 20230207520Abstract: A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.Type: ApplicationFiled: September 21, 2022Publication date: June 29, 2023Applicant: Kioxia CorporationInventors: Masayuki MIURA, Kazuma HASEGAWA, Kazushige KAWASAKI
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Patent number: 11568901Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.Type: GrantFiled: September 9, 2021Date of Patent: January 31, 2023Assignee: KIOXIA CORPORATIONInventors: Kazushige Kawasaki, Masayuki Miura, Hideko Mukaida
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Publication number: 20220293138Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.Type: ApplicationFiled: September 9, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventors: Kazushige KAWASAKI, Masayuki MIURA, Hideko MUKAIDA
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Patent number: 11270981Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.Type: GrantFiled: September 17, 2020Date of Patent: March 8, 2022Assignee: KIOXIA CORPORATIONInventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
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Publication number: 20210118898Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
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Patent number: 10892269Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: GrantFiled: May 10, 2019Date of Patent: January 12, 2021Assignee: Toshiba Memory CorporationInventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
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Publication number: 20210005580Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Applicant: Toshiba Memory CorporationInventors: Mikihiko ITO, Masaru KOYANAGI, Masafumi NAKATANI, Shinya OKUNO, Shigeki NAGASAKA, Masahiro YOSHIHARA, Akira UMEZAWA, Satoshi TSUKIYAMA, Kazushige KAWASAKI
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Patent number: 10811393Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.Type: GrantFiled: March 11, 2019Date of Patent: October 20, 2020Assignee: Toshiba Memory CorporationInventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
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Patent number: 10784648Abstract: A semiconductor device according to the present invention includes a substrate, a semiconductor laser that is provided on an upper surface of the substrate and emits laser light, a waveguide having a first conductive layer provided on the upper surface of the substrate, and a waveguide layer that is provided on the first conductive layer and guides the laser light and an embedment layer provided on the upper surface of the substrate and surrounding the semiconductor laser and the waveguide, wherein on both sides of an end part, of the waveguide, which is connected to the semiconductor laser, an exposed part is provided in which the substrate is exposed from the embedment layer by the embedment layer separated in a waveguide direction of the waveguide, and in the end part, a separation region is provided in which the first conductive layer is separated in the waveguide direction.Type: GrantFiled: May 29, 2017Date of Patent: September 22, 2020Assignee: Mitsubishi Electric CorporationInventor: Kazushige Kawasaki
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Patent number: 10777529Abstract: A semiconductor device includes a base member; a first stacked body including first semiconductor chips and second semiconductor chips stacked alternately in a first direction crossing a front surface of the base member; and a second stacked body arranged with the first stacked body in a second direction along the front surface of the base member. The second stacked body includes other first semiconductor chips and other second semiconductor chips stacked alternately in the first direction. The first stacked body includes a lowermost first semiconductor chip connected to the base member, and the second stacked body includes a lowermost second semiconductor chip connected to the base member.Type: GrantFiled: September 4, 2018Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kazushige Kawasaki
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Patent number: 10734360Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.Type: GrantFiled: September 4, 2018Date of Patent: August 4, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
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Publication number: 20200091675Abstract: A semiconductor device according to the present invention includes a substrate, a semiconductor laser that is provided on an upper surface of the substrate and emits laser light, a waveguide having a first conductive layer provided on the upper surface of the substrate, and a waveguide layer that is provided on the first conductive layer and guides the laser light and an embedment layer provided on the upper surface of the substrate and surrounding the semiconductor laser and the waveguide, wherein on both sides of an end part, of the waveguide, which is connected to the semiconductor laser, an exposed part is provided in which the substrate is exposed from the embedment layer by the embedment layer separated in a waveguide direction of the waveguide, and in the end part, a separation region is provided in which the first conductive layer is separated in the waveguide direction.Type: ApplicationFiled: May 29, 2017Publication date: March 19, 2020Applicant: Mitsubishi Electric CorporationInventor: Kazushige KAWASAKI
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Patent number: 10593649Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.Type: GrantFiled: September 4, 2018Date of Patent: March 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
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Patent number: 10510725Abstract: A semiconductor device includes a base member having a first surface and a second surface on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface; two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including semiconductor chips stacked in a second direction perpendicular to the first surface; and logic chips electrically connected respectively to the stacked bodies. Each of semiconductor chips includes first and second semiconductor layers. The first and second semiconductor layers each have an element surface and a back surface. An active element is provided on the element surface. The first semiconductor layer and the second semiconductor layer are bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.Type: GrantFiled: March 13, 2018Date of Patent: December 17, 2019Assignee: Toshiba Memory CorporationInventors: Kazushige Kawasaki, Yoichiro Kurita
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Patent number: 10497688Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.Type: GrantFiled: March 20, 2018Date of Patent: December 3, 2019Assignee: Toshiba Memory CorporationInventors: Satoshi Tsukiyama, Yoichiro Kurita, Hideo Aoki, Kazushige Kawasaki
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Publication number: 20190295985Abstract: A semiconductor device includes a base member; a first stacked body including first semiconductor chips and second semiconductor chips stacked alternately in a first direction crossing a front surface of the base member; and a second stacked body arranged with the first stacked body in a second direction along the front surface of the base member. The second stacked body includes other first semiconductor chips and other second semiconductor chips stacked alternately in the first direction. The first stacked body includes a lowermost first semiconductor chip connected to the base member, and the second stacked body includes a lowermost second semiconductor chip connected to the base member.Type: ApplicationFiled: September 4, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kazushige KAWASAKI
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Publication number: 20190295987Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.Type: ApplicationFiled: September 4, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki