Patents by Inventor Kazushige Kawasaki
Kazushige Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8209856Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter ?1 is about 95 ?m and a contact portion whose diameter ?c is about 75 ?m. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Since diameter ?c of the contact portion is substantially the same as diameter ?2 of an under bump metal at the semiconductor chip side, even if mechanical stress is applied in a direction in which the semiconductor chip is peeled off from the coreless substrate, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.Type: GrantFiled: October 5, 2009Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Hiroyuki Mori, Kazushige Kawasaki
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Publication number: 20120132463Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hiroyuki Mori, Kazushige Kawasaki
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Patent number: 8163576Abstract: A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type Ga—N substrate (1) over which a semiconductor element is formed, and an n-electrode (10) as a metal electrode formed over the back surface of the GaN substrate (1). A connection layer (20) is formed between the GaN substrate (1) and the n-electrode (10), and the connection layer (2) is composed of a material that is other than nitride semiconductors and that contains silicon.Type: GrantFiled: December 18, 2009Date of Patent: April 24, 2012Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Kazushige Kawasaki, Hitoshi Sakuma, Yuji Abe
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Publication number: 20110193126Abstract: A semiconductor light-emitting element comprises: a semiconductor substrate; a semiconductor laminated structure including a first conductivity-type semiconductor layer, an active layer, a second conductivity-type semiconductor layer, and a contact layer that are sequentially laminated on the semiconductor substrate; a ridge portion in an upper portion of the semiconductor laminated structure; a channel portion adjoining opposite sides of the ridge portion; a terrace portion adjoining opposite sides of the channel portion and, with the channel portion, sandwiching the ridge portion; a first insulating film covering the channel portion and having openings on the ridge portion and the terrace portion; a single-layer adhesive layer on the first insulating film; a Pd electrode on the ridge portion and a part of the single-layer adhesive layer and electrically connected to the contact layer of the ridge portion; and a second insulating layer covering a portion not covered by the Pd electrode of the single-layer adType: ApplicationFiled: October 26, 2010Publication date: August 11, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takafumi Oka, Shinji Abe, Kazushige Kawasaki, Hitoshi Sakuma
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Publication number: 20110177679Abstract: A method for manufacturing a semiconductor device includes preparing a substrate having a low-dislocation region and a high-dislocation region having a higher dislocation density than dislocation density of the low-dislocation region; forming an insulating film on the low-dislocation region surrounding the high-dislocation region but not covering the high-dislocation region; and forming a nitride-based semiconductor layer on the substrate, after forming the insulating film.Type: ApplicationFiled: September 24, 2010Publication date: July 21, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Akihito Ohno, Kazushige Kawasaki
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Patent number: 7981704Abstract: After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top of the waveguide ridge, and burying the SiO2 film in channels with a resist film having a surface higher than the surface of the metal cap layer of the waveguide ridge and lower than the surface of the SiO2 film of the waveguide ridge; the SiO2 film is removed by dry etching, using the resist pattern as a mask. The metal cap layer is removed by wet etching, and a p-GaN layer of the waveguide ridge is exposed to form the electrode layer.Type: GrantFiled: October 8, 2007Date of Patent: July 19, 2011Assignee: Mitsubishi Electric CorporationInventors: Shinji Abe, Kazushige Kawasaki
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Patent number: 7964424Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.Type: GrantFiled: November 5, 2008Date of Patent: June 21, 2011Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Patent number: 7911049Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.Type: GrantFiled: July 11, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Paul M. Harvey, Kazushige Kawasaki, Gen Yamada
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Patent number: 7901966Abstract: A method for manufacturing a nitride semiconductor device, comprises: epitaxially growing a semiconductor layer of a GaN-based material on the Ga surface of a GaN substrate while the GaN substrate is mounted on a substrate holder the substrate warping during the epitaxial growth so that a epitaxial deposit is deposited on the N surface of the substrate; and subjecting the N surface of the GaN substrate to vacuum suction after the epitaxial growth of the semiconductor layer; removing the epitaxial deposit from the N side of the GaN substrate after the semiconductor layer has been epitaxially grown, and before the N surface of the n-type GaN substrate is subjected to vacuum suction.Type: GrantFiled: August 4, 2009Date of Patent: March 8, 2011Assignee: Mitsubishi Electric CorporationInventors: Shinji Abe, Kazushige Kawasaki
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Patent number: 7897418Abstract: A method for manufacturing a semiconductor light emitting device includes forming an insulating film on a semiconductor substrate, the insulating film having an opening therein, forming a Pd electrode in the opening and on the insulating film, and removing the portion of the Pd electrode on the insulating film by the application of a physical force to the portion, while leaving the Pd electrode in the opening.Type: GrantFiled: December 10, 2008Date of Patent: March 1, 2011Assignee: Mitsubishi Electric CorporationInventors: Takafumi Oka, Masatsugu Kusunoki, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Patent number: 7842962Abstract: A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.Type: GrantFiled: November 16, 2005Date of Patent: November 30, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Yuji Abe
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Publication number: 20100244074Abstract: A semiconductor light-emitting device and a manufacturing method are provided, in which a metal film is deposited with positional differences between edges of an insulating film and the metal film, opposite a ridge waveguide top face, utilizing an overhanging-shaped resist pattern. An opening through the insulating film is extended in width without another masking step by etching the insulation film on the ridge waveguide top face, using the metal film as a mask. The contact area between a p-side electrode and a p-type contact layer is increased and operating voltage of the semiconductor light-emitting device is reduced.Type: ApplicationFiled: March 3, 2010Publication date: September 30, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takafumi Oka, Shinji Abe, Kazushige Kawasaki, Junichi Horie, Hitoshi Sakuma
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Patent number: 7791097Abstract: A nitride semiconductor device includes an n-type GaN substrate with a semiconductor device formed thereon and an n-type electrode which is a metal electrode formed on the rear surface of the GaN substrate. A surface modified layer and a reaction layer are interposed between the GaN substrate and n-type electrode. The surface modified layer serves as a carrier supplying layer, and is formed by causing the rear surface of the GaN substrate to react with a Si-containing plasma to be modified. The reaction layer is generated by partially removing a deposited material deposited on the surface modified layer by cleaning to generate a deposited layer and then causing Ti contained in a first metal layer and the deposited layer to partially react by heat treatment.Type: GrantFiled: July 2, 2007Date of Patent: September 7, 2010Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Hitoshi Sakuma, Junichi Horie, Toshihiko Shiga, Toshiyuki Oishi
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Patent number: 7751456Abstract: A method for manufacturing an laser diode includes: providing a wafer having thereon a semiconductor structure; depositing an SiO2 film; forming channels and a waveguide ridge between the channels in the wafer; forming an SiO2 film over the wafer; forming a resist pattern covering the SiO2 film in the channels such that the top surfaces of the resist pattern are lower than the top surface of the deposited SiO2 film on the top of the waveguide ridge, the resist pattern exposing the SiO2 film on the top of the waveguide ridge; removing the SiO2 film and the deposited SiO2 film by wet etching, using the resist pattern as a mask, to expose a p-GaN layer in the waveguide ridge; and forming an electrode layer on the top surface of the p-GaN layer.Type: GrantFiled: October 31, 2007Date of Patent: July 6, 2010Assignee: Mitsubishi Electric CorporationInventors: Kazushige Kawasaki, Toshiaki Kitano, Takafumi Oka
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Publication number: 20100151658Abstract: A method for manufacturing a nitride semiconductor device, comprises epitaxially growing a semiconductor layer of a GaN-based material on the Ga surface of a GaN substrate while the GaN substrate is mounted on a substrate holder the substrate warping during the epitaxial growth so that a epitaxial deposit is deposited on the N surface of the substrate; and subjecting the N surface of the GaN substrate to vacuum suction after the epitaxial growth of the semiconductor layer; removing the epitaxial deposit from the N side of the GaN substrate after the semiconductor layer has been epitaxially grown, and before the N surface of the n-type GaN substrate is subjected to vacuum suction.Type: ApplicationFiled: August 4, 2009Publication date: June 17, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shinji Abe, Kazushige Kawasaki
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Publication number: 20100129991Abstract: A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type Ga—N substrate (1) over which a semiconductor element is formed, and an n-electrode (10) as a metal electrode formed over the back surface of the GaN substrate (1). A connection layer (20) is formed between the GaN substrate (1) and the n-electrode (10), and the connection layer (2) is composed of a material that is other than nitride semiconductors and that contains silicon.Type: ApplicationFiled: December 18, 2009Publication date: May 27, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi SHIOZAWA, Kyozo Kanamoto, Kazushige Kawasaki, Hitoshi Sakuma, Yuji Abe
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Patent number: 7714439Abstract: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.Type: GrantFiled: August 24, 2007Date of Patent: May 11, 2010Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Hitoshi Sakuma, Kazushige Kawasaki, Toshihiko Shiga, Toshiyuki Oishi
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Publication number: 20100096744Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter ?1 is about 95 ?m and a contact portion whose diameter ?c is about 75 ?m. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Since diameter ?c of the contact portion is substantially the same as diameter ?2 of an under bump metal at the semiconductor chip side, even if mechanical stress is applied in a direction in which the semiconductor chip is peeled off from the coreless substrate, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.Type: ApplicationFiled: October 5, 2009Publication date: April 22, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hiroyuki Mori, Kazushige Kawasaki
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Patent number: 7691655Abstract: Method for manufacturing a semiconductor optical device includes forming an epitaxial structure containing at least an active layer which can emit light, of a III-V group semiconductor material; forming an insulating layer over the epitaxial structure, which prevents the V group element from escaping from the epitaxial structure during heat treatment; heat treating the epitaxial structure at at least 800 degrees C.; and removing the insulating layer, thereby enhancing the reliability of the device.Type: GrantFiled: November 2, 2006Date of Patent: April 6, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazushige Kawasaki, Kimio Shigihara
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Patent number: 7687391Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.Type: GrantFiled: September 27, 2006Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Paul M. Harvey, Kazushige Kawasaki, Gen Yamada