Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: A semiconductor device includes a base member having a first surface and a second surface on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface; two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including semiconductor chips stacked in a second direction perpendicular to the first surface; and logic chips electrically connected respectively to the stacked bodies. Each of semiconductor chips includes first and second semiconductor layers. The first and second semiconductor layers each have an element surface and a back surface. An active element is provided on the element surface. The first semiconductor layer and the second semiconductor layer are bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.

Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.

Abstract: A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: A distributed feedback laser diode includes a substrate, an active layer located above and supported by the substrate, and a diffraction grating diffracting light generated in the active layer. The diffraction grating includes features and each feature includes dots. Each of the dots has a length less than 2.5 ?m.

Abstract: A method of manufacturing a semiconductor laser device includes the steps of: preparing the semiconductor laser bar body including a top surface, an undersurface, two mutually opposing facets, and two mutually opposing side faces, performing a coating step to form a coating film on the facet, and performing a division step after the coating step. The division step performs scribing on and divides the semiconductor laser bar body. A groove is formed on the facet by denting the facet, or is formed in the coating film by exposing a part of the facet, and the groove extends from the top surface to the undersurface. A width of the groove is 20 ?m. Scribing is performed on the top surface or the undersurface so that a scribed track or an extended line of the scribed track meets the groove.

Abstract: According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.

Abstract: A method of manufacturing a semiconductor laser device includes the steps of: preparing the semiconductor laser bar body including a top surface, an undersurface, two mutually opposing facets, and two mutually opposing side faces, performing a coating step to form a coating film on the facet, and performing a division step after the coating step. The division step performs scribing on and divides the semiconductor laser bar body. A groove is formed on the facet by denting the facet, or is formed in the coating film by exposing a part of the facet, and the groove extends from the top surface to the undersurface. A width of the groove is 20 ?m. Scribing is performed on the top surface or the undersurface so that a scribed track or an extended line of the scribed track meets the groove.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.

Abstract: A distributed feedback laser diode includes a substrate, an active layer located above and supported by the substrate, and a diffraction grating diffracting light generated in the active layer. The diffraction grating includes features and each feature includes dots. Each of the dots has a length less than 2.5 ?m.

Abstract: A distributed feedback laser diode includes a substrate, an active layer located above and supported by the substrate, and a diffraction grating having a first feature and a second feature and being configured to diffract light generated in the active layer, the second feature being shorter than the first feature and facing a central portion of the first feature.

Abstract: According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion.

Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.