Abstract: A communication device to be coupled to a transmission device with MC-LAG, the communication device includes a first output port coupled to an other communication device within a first route, a second output port within a second route, an iTAS device arranged in each of the first output port and the second output port, and configured to preferentially output a high priority flow, based on a set an iTAS period, a memory, and a processor coupled to the memory and configured to acquire a first iTAS period set to the iTAS device arranged in the first output port and a second iTAS period set to an iTAS device arranged in a third output port in the other communication device within the first route, and set an iTAS period of the iTAS device arranged in the second output port, based on the first and second iTAS periods.

Abstract: A packet processing apparatus includes a memory, a processor, a first gate, and a second gate. The memory stores a plurality of allocation patterns for allocating an upstream or downstream of a link direction for each subframe within a predetermined period. The processor obtains a periodicity pattern of a high-priority packet for each of time slots within the subframe. The first gate opens and closes, for each of the time slots within the subframe, output of the high-priority packet. The second gate opens and closes, for each of the time slots within the subframe, output of a low-priority packet. The processor sets gate states of the first gate and the second gate for a predetermined time slot within the subframe in the same link direction as the periodicity pattern to a priority state in which the high-priority packet is preferentially output according to the periodicity pattern.

Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.

Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.

Abstract: A packet processing device includes a first unit, a second unit, and a switching unit. The first unit counts the number of arrived packets in a first period that is from the time slot present after a priority section up to the end of the initial time slot in the subsequently-arriving priority section. When the counted number of arrived packets is positive, the first unit determines that forward mismatch has occurred in an observation cycle. The second unit counts the number of arrived packets in a second period which is from the time slot present immediately after the priority section in the first period of time up to the end of the initial time slot of burst sections in the subsequently-arriving priority section. When the counted number of arrived packets is “0”, the second unit determines that backward mismatch has occurred in the observation cycle.

Abstract: A packet processing apparatus includes a plurality of queues that store received packets according to types of the received packets; and a processor coupled to the plurality of queues and configured to: collect information on packet quantity of received packets in each time slot, identify a periodicity pattern of the received packets based on the packet quantity of the received packets in each time slot, based on the identified periodicity pattern of the received packets, identify a time slot section where received packets of a predetermined type are to be outputted preferentially, and control opening and closing of each of the plurality of queues in the identified time slot section.

Abstract: A packet processing apparatus includes a memory, a processor, a first gate, and a second gate. The memory stores a plurality of allocation patterns for allocating an upstream or downstream of a link direction for each subframe within a predetermined period. The processor obtains a periodicity pattern of a high-priority packet for each of time slots within the subframe. The first gate opens and closes, for each of the time slots within the subframe, output of the high-priority packet. The second gate opens and closes, for each of the time slots within the subframe, output of a low-priority packet. The processor sets gate states of the first gate and the second gate for a predetermined time slot within the subframe in the same link direction as the periodicity pattern to a priority state in which the high-priority packet is preferentially output according to the periodicity pattern.

Abstract: A packet processing device includes a memory; and a processor configured to acquire an amount of packets arriving in each first section length as a first sampling value, determine a plurality of temporary periods based on a multiple of the first section length, calculate, for each of the temporary periods, a statistical value obtained by quantifying a bias in the amount of packets arriving in each first section length based on the first sampling value, estimate the temporary period having a maximum statistical value as a neighborhood period, acquire an amount of packets arriving in each second section length as a second sampling value, determine a plurality of neighborhood temporary periods around the neighborhood period, calculate a statistical value for each neighborhood temporary period based on the second sampling value, and estimate the neighborhood temporary period having the maximum statistical value as a true period of the arriving packets.

Abstract: A packet processing device includes a first unit, a second unit, and a switching unit. The first unit counts the number of arrived packets in a first period that is from the time slot present after a priority section up to the end of the initial time slot in the subsequently-arriving priority section. When the counted number of arrived packets is positive, the first unit determines that forward mismatch has occurred in an observation cycle. The second unit counts the number of arrived packets in a second period which is from the time slot present immediately after the priority section in the first period of time up to the end of the initial time slot of burst sections in the subsequently-arriving priority section. When the counted number of arrived packets is “0”, the second unit determines that backward mismatch has occurred in the observation cycle.

Abstract: There is provided a transmission apparatus including at least one memory in which a first data including a first destination information and a second data including a second destination information are stored, and at least one processor coupled to the at least one memory and the at least one processor configured to control the at least one memory to output the first data and the second data stored in the at least one memory according to a set rate, and control the set rate to output one of the first data and the second data according to a priority degree.

Abstract: A packet processing apparatus includes a plurality of queues that store received packets according to types of the received packets; and a processor coupled to the plurality of queues and configured to: collect information on packet quantity of received packets in each time slot, identify a periodicity pattern of the received packets based on the packet quantity of the received packets in each time slot, based on the identified periodicity pattern of the received packets, identify a time slot section where received packets of a predetermined type are to be outputted preferentially, and control opening and closing of each of the plurality of queues in the identified time slot section.

Abstract: A packet processing device includes a memory; and a processor configured to acquire an amount of packets arriving in each first section length as a first sampling value, determine a plurality of temporary periods based on a multiple of the first section length, calculate, for each of the temporary periods, a statistical value obtained by quantifying a bias in the amount of packets arriving in each first section length based on the first sampling value, estimate the temporary period having a maximum statistical value as a neighborhood period, acquire an amount of packets arriving in each second section length as a second sampling value, determine a plurality of neighborhood temporary periods around the neighborhood period, calculate a statistical value for each neighborhood temporary period based on the second sampling value, and estimate the neighborhood temporary period having the maximum statistical value as a true period of the arriving packets.

Abstract: There is provided a transmission apparatus including at least one memory in which a first data including a first destination information and a second data including a second destination information are stored, and at least one processor coupled to the at least one memory and the at least one processor configured to control the at least one memory to output the first data and the second data stored in the at least one memory according to a set rate, and control the set rate to output one of the first data and the second data according to a priority degree.

Abstract: A traffic control apparatus at which packets of a plurality of packet flows arrive includes a plurality of buffers corresponding to a plurality of times, a selector configured to read a packet accumulated in one of the plurality of buffers corresponding to a current time, and a scheduler configured to decide one of the plurality of buffers to accumulate a packet of each of the plurality of packet flows. The scheduler attempts, for each of the plurality of packet flows, accumulation of packets which are reached during a predetermined period under a condition that, as quantity of packets accumulated in the plurality of buffers is larger, the number of buffers into which packets can be accumulated becomes smaller after the predetermined period.

Abstract: An apparatus includes a memory storing a table including packet identification information and information indicating a process corresponding to the packet identification information, a unit to search for a process corresponding to packet identification information of a received packet from the table, a unit to acquire table candidates that have different types and in which all packets identified by new identification information for a packet and existing identification information for a packet are retrievable from the table candidates, based on the existing packet identification information and the new packet identification information when a addition request of a new entry including the new identification information for a packet is received, and a unit to select a table used for a search among the table candidates based on the number of packet identification information stored in each of the table candidates.

Abstract: A communication device includes: a plurality of output ports; a plurality of queues in which packets are stored so as to be sorted into groups of packets that are output from an identical output port in an identical time period, from among the plurality of output ports; a plurality of first selectors that respectively corresponds to the plurality of output ports, and each of which switches a queue from which packets that are output from the output port are read, between the plurality of queues each time the time period elapses; and a second selector that switches a first selector from which packets are output, between the plurality of first selectors, at time intervals in accordance with output rates of packets of the plurality of output ports.

Abstract: A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.

Abstract: A bandwidth control device includes: a management unit to subtract, when a first bandwidth control device (first device) or one or more second bandwidth control devices (second devices) allow a packet to pass, an amount of the passed packet from a permissible passage amount to be passed the first device; and a correction unit to correct the permissible passage amount of the first device or a threshold value of the first device based on a result of a comparison between a passage amount of packets passed the first device and passage amounts of packets passed the second devices, wherein the first device determines whether a packet is to be allowed to pass through or not based on a result of a comparison between the permissible passage amount and the threshold value and allows the packet to pass or discard the packet according to the determination result.

Abstract: There is provided a communication device including: a memory configured to store a procedure for controlling a transmission rate of a packet based on an amount of tokens; a processor configured to execute the procedure by: requesting the amount of tokens to a network management device; and supplying the amount of tokens supplied from the network management device in response to the requesting, to other communication devices belonging to a group to which the communication device also belongs; and a hardware processor configured to transfer request processing and supply processing of the amount of tokens which are executed by the processor, to one of the other communication devices belonging to the group, that satisfies a delay condition related to a delay time of communication and a load condition related to a load of processing in the group.

Abstract: An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.