Abstract: A switching apparatus for learning a source address set in a packet in an address learning table and delivering a packet on the basis of an address learned in the address learning table includes an address learning unit for limiting a number of learned addresses such that a number of learned addresses for each user group in the address learning table is equal to or less than an address learning upper limit value for the user group.

Abstract: The present invention relates to the rate control system of a TCP layer in communications conducted between terminals 1 and 3 via a base station 2 using a wireless link. An object of the present invention is to avoid the fruitless reduction of throughput in communications conducted via a wireless link. If the discard of a packet transmitted from the base station 2 to the terminal 3 via a wireless link is detected when the packet is transmitted from the terminal 1 to the terminal 3, the base station or terminal 3 is provided with means for notifying the terminal 1 of a wireless packet discard using a TCP layer. The terminal 1 is configured in such a way that if the wireless packet discard notification is received, a TCP layer control unit 10 does not exercise slow-start control at the time of re-transmission and re-transmits the discarded packet at a rate adopted before the reception of the notification.

Abstract: An inquiry responding apparatus includes a receiving means for receiving an inquiry, a first database for storing a response to the inquiry, a determining means for determining whether or not said first database can be searched for the response to the inquiry, a searching means for searching said first database for the response to the inquiry when the determining means determines that said first database can be searched, a transmitting means for transmitting the inquiry to an external information processing device when said determining means determines that said first database cannot be searched, a second receiving means for receiving a response to the inquiry which is transmitted from the external information processing device, a displaying means for displaying one of the response obtained by said searching means and the response received by the second receiving means.

Abstract: A cell transmitted from a transmitting terminal is multicast to a plurality of receiving terminals. The plurality of receiving terminals respectively transmit B-RM cells to the transmitting terminal. Each of the B-RM cells is assigned an ER value. An ER value calculating unit calculates an average value of the ER values which are respectively assigned to the B-RM cells from the plurality of receiving terminals. A B-RM cell processing unit transfers to the transmitting terminal a B-RM cell to which the ER value calculated by the ER value calculating unit is assigned. The transmitting terminal controls the transmission rate of a multicast communication with the plurality of receiving terminals according to the ER value assigned to the received B-RM cell.

Abstract: A node in a ring network system in which a plurality of nodes are connected in loop through a ring transmission path, includes a storage unit having storage areas according to insertion nodes at which arrived packets are inserted into the ring transmission path, and accumulating the packets in the storage areas according to the insertion nodes, and a read control unit reading the packets in a fair way on the basis of predetermined weights respectively from the storage areas according to the insertion nodes.

Abstract: The present invention relates to a buffer control apparatus and method.

Abstract: A bottleneck path prediction/storage unit predicts a bottleneck path, that is, a logic circuit whose transmission rate is limited by a cell switching unit other than a predetermined cell switching unit, the logic circuit being one of the logic circuits which use a predetermined physical circuit in the predetermined cell switching unit. An ER computation unit sets an ER value in a resource management cell transferred through the physical circuit based on a state (number of active logic circuits) of the logic circuit which uses the physical circuit and information about the bottleneck path predicted by the bottleneck path prediction/storage unit.