Patents by Inventor Kazuto Nishimura

Kazuto Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160308696
    Abstract: An apparatus includes a plurality of first circuits that duplicate and transmit a packet, a memory that store the packet correspond to one of the plurality of first circuit, and a second circuit that select one of the plurality of first circuits, using cumulative remaining copy amount correspond to each of the plurality of first circuits that are calculated based on the packet accumulation in the memory.
    Type: Application
    Filed: March 9, 2016
    Publication date: October 20, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Kazuto NISHIMURA
  • Publication number: 20150312156
    Abstract: A bandwidth control device includes: a management unit to subtract, when a first bandwidth control device (first device) or one or more second bandwidth control devices (second devices) allow a packet to pass, an amount of the passed packet from a permissible passage amount to be passed the first device; and a correction unit to correct the permissible passage amount of the first device or a threshold value of the first device based on a result of a comparison between a passage amount of packets passed the first device and passage amounts of packets passed the second devices, wherein the first device determines whether a packet is to be allowed to pass through or not based on a result of a comparison between the permissible passage amount and the threshold value and allows the packet to pass or discard the packet according to the determination result.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 29, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi KITADA, Kazuto Nishimura
  • Patent number: 9154390
    Abstract: A packet relay apparatus includes a first packet processing circuit and a second packet processing circuit. The first packet processing circuit executes, discarding data packets from among data packets, and transferring the rest of the data packets to the second packet processing circuit, counting discard number of the data packets, determining whether or not the discard number is equal to or greater than a threshold and transferring, if the discard number is equal to or greater than the threshold, a discard number information packet including discard number information indicating the discard number to the second packet processing circuit. The second packet processing circuit executes discarding data packets from among the data packets, counting discard number of the data packets and collecting the discard number counted by the second packet processing circuit and the discard number indicated by the discard number information included in the discard number information packet.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 6, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Kitada, Kazuto Nishimura
  • Patent number: 9143453
    Abstract: A relay apparatus that transfers data with an identifier corresponding to a transfer rate attached thereto and stores data as a transfer target to adjust the transfer rate, the relay apparatus includes multiple buffers that are respectively associated with multiple time regions that serve as targets to be successively read from a current point of time onward, each buffer having a capacity to store an amount of data determined in accordance with the transfer rate of the identifier, and a controller that reduces a size of a buffer corresponding to a second time region to be smaller than a size of a buffer corresponding to a first time region prior to the second time region in accordance with a time difference between the current point of time and the second time region.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: September 22, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Kazuto Nishimura
  • Patent number: 9124492
    Abstract: A packet relay apparatus includes a first packet processing circuit and a second packet processing circuit. The first packet processing circuit executes, discarding data packets from among data packets, and transferring the rest of the data packets to the second packet processing circuit, counting discard number of the data packets, determining whether or not the discard number is equal to or greater than a threshold and transferring, if the discard number is equal to or greater than the threshold, a discard number information packet including discard number information indicating the discard number to the second packet processing circuit. The second packet processing circuit executes discarding data packets from among the data packets, counting discard number of the data packets and collecting the discard number counted by the second packet processing circuit and the discard number indicated by the discard number information included in the discard number information packet.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Kitada, Kazuto Nishimura
  • Publication number: 20150124836
    Abstract: A communication device includes: a plurality of output ports; a plurality of queues in which packets are stored so as to be sorted into groups of packets that are output from an identical output port in an identical time period, from among the plurality of output ports; a plurality of first selectors that respectively corresponds to the plurality of output ports, and each of which switches a queue from which packets that are output from the output port are read, between the plurality of queues each time the time period elapses; and a second selector that switches a first selector from which packets are output, between the plurality of first selectors, at time intervals in accordance with output rates of packets of the plurality of output ports.
    Type: Application
    Filed: October 16, 2014
    Publication date: May 7, 2015
    Inventor: Kazuto NISHIMURA
  • Publication number: 20150078395
    Abstract: A traffic control apparatus at which packets of a plurality of packet flows arrive includes a plurality of buffers corresponding to a plurality of times, a selector configured to read a packet accumulated in one of the plurality of buffers corresponding to a current time, and a scheduler configured to decide one of the plurality of buffers to accumulate a packet of each of the plurality of packet flows. The scheduler attempts, for each of the plurality of packet flows, accumulation of packets which are reached during a predetermined period under a condition that, as quantity of packets accumulated in the plurality of buffers is larger, the number of buffers into which packets can be accumulated becomes smaller after the predetermined period.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 19, 2015
    Inventor: Kazuto Nishimura
  • Patent number: 8953454
    Abstract: An apparatus for policing traffic in a communication network is provided. The apparatus includes a packet distributor, a plurality of policing units, and a token management unit. The packet distributor evenly distributes packets that have arrived at the apparatus. Each policing unit determines whether a packet distributed from the packet distributor is permitted to be passed or discarded in accordance with an amount of tokens remaining in a first token bucket provided for the each policing unit, and issues a token request for requesting supply of tokens when an amount of tokens remaining in the first token bucket falls below a first threshold value. The token management unit supplies tokens in units of a predetermined amount to the first token bucket for which the token request has been issued, in accordance with an amount of tokens remaining in a second bucket provided for the token management unit.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Patent number: 8937962
    Abstract: A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: January 20, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Tomonaga, Kazuto Nishimura
  • Patent number: 8811376
    Abstract: A packet transmitting apparatus according to the present invention includes a plurality of ports. When the same unlearned packets have arrived at the plurality of ports, the packet transmitting apparatus judges through packet processing section that the first arrived one of the packets is a previous arrival packet. Then, through previous arrival group judging section, the packet transmitting apparatus selects from the plurality of ports a plurality of ports satisfying a previous arrival port condition for determining a port at which the previous arrival packet arrives as a previous arrival port. The packet transmitting apparatus judges the thus selected plurality of ports as the previous arrival ports having an equal previous arrival characteristic of packets, and includes the ports in a previous arrival port group.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Patent number: 8780719
    Abstract: A packet relay apparatus relaying a packet exchanged between communication apparatuses with a connection established is provided. The packet relay apparatus includes a buffer for storing a packet selected from among arrival packets so that a transfer of the selected packet is to be suspended, and a congestion controller for monitoring, after the storage of the packet on the buffer, a packet passing through the packet relay apparatus, and causing the packet, stored on the buffer, to be transmitted at a timing responsive to a passage status of a packet having the same connection as the connection of the packet stored on the buffer.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 15, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Publication number: 20140192819
    Abstract: A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.
    Type: Application
    Filed: December 9, 2013
    Publication date: July 10, 2014
    Applicant: Fujitsu Limited
    Inventors: Kazuto NISHIMURA, Atsushi Kitada, Hiroshi Tomonaga, Tsutomu Noguchi
  • Publication number: 20140177443
    Abstract: A relay apparatus that transfers data with an identifier corresponding to a transfer rate attached thereto and stores data as a transfer target to adjust the transfer rate, the relay apparatus includes multiple buffers that are respectively associated with multiple time regions that serve as targets to be successively read from a current point of time onward, each buffer having a capacity to store an amount of data determined in accordance with the transfer rate of the identifier, and a controller that reduces a size of a buffer corresponding to a second time region to be smaller than a size of a buffer corresponding to a first time region prior to the second time region in accordance with a time difference between the current point of time and the second time region.
    Type: Application
    Filed: November 1, 2013
    Publication date: June 26, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kazuto NISHIMURA
  • Patent number: 8717891
    Abstract: A shaping apparatus includes a plurality of buffers that are set with a writable upper limit size and a buffer where a read processing is carried out is switched every predetermined time. A flow information table includes specific information for specifying a buffer in which input data should be written for each of flows of the input data, maximum amount information indicating a maximum data amount writable in each of the plurality of buffers for each of the flows, and remaining amount information indicating a remaining data amount writable in the buffer specified by the specific information for each of the flows. A shaper writes the input data in the buffer specified by the specific information among the plurality of buffers for each of the flows.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Patent number: 8602890
    Abstract: To provide a game device capable of improving reality regarding an operation of a game in which an attack on one or more attack targets is performed. Remaining number-of-times information storage means (70) stores remaining number-of-times information that indicates a remaining number of times an attack on one or more attack targets can be performed. Display means (74) displays a screen that includes a first image, containing a plurality of reference regions, and a second image. Image moving means (72) moves at least one of the first image and the second image according to a direction instructing operation of a player. Remaining number-of-times information update means (76) increases the remaining number of times the attack on one or more attack target can be performed based on a number of one or more reference regions included in a superposition region in which the first image and the second image are superposed on each other.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: December 10, 2013
    Assignee: Konami Digital Entertainment Co., Ltd.
    Inventors: Mitsuhiro Nomi, Fumiaki Oshita, Kazuto Nishimura, Kazuhiko Ninomiya, Takaharu Ikeda
  • Patent number: 8582467
    Abstract: A method for preventing a control packet loop in a network realizing node redundancy or circuit redundancy based on a rapid spanning tree protocol or a multiple spanning tree protocol is disclosed. The method includes the steps of: detecting a loop of a control packet of the rapid spanning tree protocol or the multiple spanning tree protocol; and discarding the control packet by which the loop is detected so as to prevent occurrence of the loop of the control packet.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Masaki Hirota, Kazuto Nishimura, Yasushi Sasakawa, Kou Takatori
  • Patent number: 8576850
    Abstract: A band control apparatus including: a buffer memory configured to hold and output data units on a first-in first-out basis; a counter memory configured to hold a counter value; and a processor configured to add a value to the counter value on a basis of a rule, reduce, when a first one of the data units is output from the buffer memory, cause, when a first condition of a total size of the data units being smaller than a buffer threshold is satisfied, the first data unit to be output when a second condition that the counter value is larger than the size of the first data unit is satisfied and the counter value is larger than a counter threshold, and cause, when the first condition is not satisfied, the data units to be output in sequence with the first data unit first, until a third condition is satisfied.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Patent number: 8553538
    Abstract: A packet relay device including a plurality of queues which store packets waiting to be transmitted, a congestion detection unit which detects a congestion state of the plurality of queues and selects one or more queues from among the plurality of queues based on the congestion state, a distribution unit which separates a packet addressed to one or more of the queues selected by the congestion detection unit from a sequence of packets before being stored in the plurality of queues, and a discard unit which discards, at a prescribed probability, a packet addressed to one or more of the queues separated by the distribution unit.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Limited
    Inventor: Kazuto Nishimura
  • Publication number: 20130242742
    Abstract: An apparatus for policing traffic in a communication network is provided. The apparatus includes a packet distributor, a plurality of policing units, and a token management unit. The packet distributor evenly distributes packets that have arrived at the apparatus. Each policing unit determines whether a packet distributed from the packet distributor is permitted to be passed or discarded in accordance with an amount of tokens remaining in a first token bucket provided for the each policing unit, and issues a token request for requesting supply of tokens when an amount of tokens remaining in the first token bucket falls below a first threshold value. The token management unit supplies tokens in units of a predetermined amount to the first token bucket for which the token request has been issued, in accordance with an amount of tokens remaining in a second bucket provided for the token management unit.
    Type: Application
    Filed: January 28, 2013
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Kazuto Nishimura
  • Publication number: 20130229925
    Abstract: A packet relay apparatus includes a first packet processing circuit and a second packet processing circuit. The first packet processing circuit executes, discarding data packets from among data packets, and transferring the rest of the data packets to the second packet processing circuit, counting discard number of the data packets, determining whether or not the discard number is equal to or greater than a threshold and transferring, if the discard number is equal to or greater than the threshold, a discard number information packet including discard number information indicating the discard number to the second packet processing circuit. The second packet processing circuit executes discarding data packets from among the data packets, counting discard number of the data packets and collecting the discard number counted by the second packet processing circuit and the discard number indicated by the discard number information included in the discard number information packet.
    Type: Application
    Filed: November 26, 2012
    Publication date: September 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi Kitada, Kazuto Nishimura