Patents by Inventor Kazuto Tsuji
Kazuto Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7923835Abstract: An electronic device has a substrate that has first and second peripheral portions. The first peripheral portion provides a shearing position for separation. The electronic device has a plurality of wiring layers one of which forms a functional surface wiring on the substrate, an electronic element mounted on the substrate, and an encapsulation member formed over the substrate and the electronic element. The surface wiring is selectively disposed under the encapsulation member and in an area adjacent to the second peripheral portion.Type: GrantFiled: January 23, 2008Date of Patent: April 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Yoshihiro Kubota, Shirou Youda, Kazuto Tsuji
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Patent number: 7476811Abstract: A semiconductor device includes: a semiconductor element; a circuit substrate having a cavity at a center thereof; a heat radiating member having the semiconductor element bonded at a central portion thereof; and a sealing resin configured to seal the semiconductor element in the cavity. A configuration is provided such that a bonding resin may be disposed in a gap portion which communicates with the cavity between the circuit substrate and the heat radiating member, and by means of a bonding force of the bonding resin, the heat radiating member is permanently fixed to the circuit substrate.Type: GrantFiled: March 14, 2005Date of Patent: January 13, 2009Assignee: Fujitsu LimitedInventors: Yoshihiro Kubota, Kazuto Tsuji, Sumikazu Hosoyamada
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Publication number: 20080174005Abstract: An electronic device has a substrate that has first and second peripheral portions. The first peripheral portion provides a shearing position for separation. The electronic device has a plurality of wiring layers one of which forms a functional surface wiring on the substrate, an electronic element mounted on the substrate, and an encapsulation member formed over the substrate and the electronic element. The surface wiring is selectively disposed under the encapsulation member and in an area adjacent to the second peripheral portion.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: FUJITSU LIMITEDInventors: Yoshihiro Kubota, Shirou Youda, Kazuto Tsuji
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Patent number: 7362759Abstract: Method and apparatus for encoding overhead is described. More particularly, on a receive side channels are multiplexed, and a channel is selected for overhead to process. Transport Overhead and Path Overhead are parsed out and provided to an overhead extractor for encoding. Overhead is encoded according to channel number, frame number, row location and column location (“encoded information”), where either row location or column location is dependent on frame number. On the transmit side, encoded overhead is received at an overhead inserter and parsed back for line output by decoding the encoded information.Type: GrantFiled: September 27, 2001Date of Patent: April 22, 2008Assignee: Intel CorporationInventors: Michael Yo-Yun Ho, Oon-Sim Ang, Barry Kazuto Tsuji, Oreste Basil Varelas
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Patent number: 7361980Abstract: A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.Type: GrantFiled: May 26, 2005Date of Patent: April 22, 2008Assignee: Fujitsu LimitedInventors: Sumikazu Hosoyamada, Kazuto Tsuji, Yoshihiro Kubota
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Publication number: 20070221978Abstract: The semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a heat diffusion member mounted on the substrate while covering the semiconductor element, and a resin seal for covering the semiconductor element. An integrated capacitor is mounted on the heat diffusion member in an opposed relationship to the semiconductor element and electrically connected to the semiconductor element. The integrated capacitor and the semiconductor element are electrically connected over a distance as shortest as possible. The heat diffusion member includes a first conductive layer and a second conductive layer isolated from each other by an insulating layer, some terminals of the integrated capacitor are connected to the corresponding terminals of the substrate through the first conductive layer, and the other terminals of the integrated capacitor are connected to the corresponding terminals of the substrate through the second conductive layer.Type: ApplicationFiled: May 16, 2007Publication date: September 27, 2007Applicant: FUJITSU LIMITEDInventor: Kazuto Tsuji
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Publication number: 20070114642Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Patent number: 7193320Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: GrantFiled: January 28, 2003Date of Patent: March 20, 2007Assignee: Fujitsu LimitedInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Patent number: 7144754Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: GrantFiled: June 1, 2004Date of Patent: December 5, 2006Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Publication number: 20060137902Abstract: A semiconductor device includes: a semiconductor element; a circuit substrate having a cavity at a center thereof; a heat radiating member having the semiconductor element bonded at a central portion thereof; and a sealing resin configured to seal the semiconductor element in the cavity. A configuration is provided such that a bonding resin may be disposed in a gap portion which communicates with the cavity between the circuit substrate and the heat radiating member, and by means of a bonding force of the bonding resin, the heat radiating member is permanently fixed to the circuit substrate.Type: ApplicationFiled: March 14, 2005Publication date: June 29, 2006Applicant: FUJITSU LIMITEDInventors: Yoshihiro Kubota, Kazuto Tsuji, Sumikazu Hosoyamada
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Patent number: 7042102Abstract: In a semiconductor device, bonding-wires can be applied parallel to each other to electrodes of high-speed signal lines when mounting a highly densified semiconductor element on a low-cost substrate while reducing a length of the bonding-wires. An impedance-matched substrate having wiring that impedance-matched with circuits of a semiconductor element is mounted on a substrate. A plurality of first metal wires connect between first electrodes of the semiconductor element and electrodes of the substrate. A plurality of second metal wires connect between second electrodes of the semiconductor element and first electrodes of the impedance-matched substrate. A plurality of third metal wires connect between second electrodes of the impedance-matched substrate and electrodes of the substrate. The second metal wires extend parallel to each other, and the third metal wires also extend parallel to each other.Type: GrantFiled: October 25, 2004Date of Patent: May 9, 2006Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshihiro Kubota, Kenji Asada, Sumikazu Hosoyamada
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Patent number: 7042910Abstract: Method and apparatus is described for decoupling data from a clock signal and recoupling the data to a different clock signal for subsequent synchronous processing by a pointer processor. More particularly, on a receive or drop side, one buffer is configured to store payload pointers and a synchronous payload envelope arriving clocked by a line clock signal, while another buffer is configure to store TOH or SOH arriving clocked by the line clock signal. Each buffer clocks out such stored information off of a same system clock signal, such as a drop clock signal. On a transmit or add side, a buffer is configured to store payload pointers and a synchronous payload envelope. This buffer clocks in such stored information off of a system clock signal, such as an add clock signal, and clocks out such stored information off of a transmit reference clock signal.Type: GrantFiled: August 14, 2001Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Oon-Sim Ang, Barry Kazuto Tsuji, Oreste Basil Varelas
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Publication number: 20050280034Abstract: A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.Type: ApplicationFiled: May 26, 2005Publication date: December 22, 2005Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Kazuto Tsuji, Yoshihiro Kubota
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Publication number: 20050269701Abstract: In a semiconductor device, bonding-wires can be applied parallel to each other to electrodes of high-speed signal lines when mounting a highly densified semiconductor element on a low-cost substrate while reducing a length of the bonding-wires. An impedance-matched substrate having wiring that impedance-matched with circuits of a semiconductor element is mounted on a substrate. A plurality of first metal wires connect between first electrodes of the semiconductor element and electrodes of the substrate. A plurality of second metal wires connect between second electrodes of the semiconductor element and first electrodes of the impedance-matched substrate. A plurality of third metal wires connect between second electrodes of the impedance-matched substrate and electrodes of the substrate. The second metal wires extend parallel to each other, and the third metal wires also extend parallel to each other.Type: ApplicationFiled: October 25, 2004Publication date: December 8, 2005Inventors: Kazuto Tsuji, Yoshihiro Kubota, Kenji Asada, Sumikazu Hosoyamada
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Patent number: 6856017Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: GrantFiled: November 17, 1999Date of Patent: February 15, 2005Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Publication number: 20040219719Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: ApplicationFiled: June 1, 2004Publication date: November 4, 2004Applicant: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Patent number: 6798031Abstract: A semiconductor device includes a resin housing provided with a functional part, a wire pattern made of a conductive material and molded in the resin housing, a part of the wire pattern being exposed from the resin housing, an electronic part connected with the wire pattern in a state where the electronic parts is molded in the resin housing, and a semiconductor element connected to the part of the wire pattern being exposed from the resin housing. The semiconductor element provides a designated function in cooperation with a functional part of the resin housing.Type: GrantFiled: March 28, 2002Date of Patent: September 28, 2004Assignee: Fujitsu LimitedInventors: Toshiyuki Honda, Kazuto Tsuji, Masanori Onodera, Hiroshi Aoki, Izumi Kobayashi, Susumu Moriya, Hiroshi Kaiya
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Patent number: 6696754Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: GrantFiled: August 8, 2002Date of Patent: February 24, 2004Assignee: Fujitsu LimitedInventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
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Publication number: 20030222344Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 28, 2003Publication date: December 4, 2003Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Publication number: 20030164544Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: ApplicationFiled: August 8, 2002Publication date: September 4, 2003Applicant: FUJITSU LIMITEDInventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki