Patents by Inventor Kazuto Tsuji
Kazuto Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5891758Abstract: A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board.Type: GrantFiled: October 31, 1997Date of Patent: April 6, 1999Assignee: Fujitsu Limited, Ltd.Inventors: Toshiyuki Honda, Akihiro Oku, Takanori Watanabe, Kazuto Tsuji, Yoshiyuki Yoneda
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Patent number: 5861669Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.Type: GrantFiled: June 7, 1995Date of Patent: January 19, 1999Assignee: Fujitsu LimitedInventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
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Patent number: 5842628Abstract: A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.Type: GrantFiled: April 8, 1996Date of Patent: December 1, 1998Assignee: Fujitsu LimitedInventors: Ryuji Nomoto, Kazuto Tsuji, Mitsutaka Sato, Junichi Kasai
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Patent number: 5831332Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.Type: GrantFiled: October 29, 1996Date of Patent: November 3, 1998Assignee: Fujitsu LimitedInventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
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Patent number: 5808357Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor parts which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode ads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.Type: GrantFiled: June 7, 1995Date of Patent: September 15, 1998Assignee: Fujitsu LimitedInventors: Hideharu Sakoda, Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5804468Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.Type: GrantFiled: November 21, 1995Date of Patent: September 8, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
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Patent number: 5786985Abstract: A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.Type: GrantFiled: November 15, 1996Date of Patent: July 28, 1998Assignee: Fujitsu LimitedInventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto, Katsuhiro Hayashida, Mitsutaka Sato, Hiroshi Yoshimura, Tadashi Uno, Kosuke Otokita, Tetsuya Fujisawa
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Patent number: 5767527Abstract: A semiconductor device includes a rigid member embedded in a resin package body for supporting thereon outer leads that extend from the resin package body and test pads provided on the outer leads for testing the semiconductor device.Type: GrantFiled: July 5, 1995Date of Patent: June 16, 1998Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5750421Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: May 12, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5736428Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: April 7, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5703398Abstract: A semiconductor integrated circuit device includes a semiconductor chip supported by a stage, leads electrically connected to the semiconductor chip, first and second heat radiating members provided on first and second sides of the semiconductor chip, and a resin package body completely sealing the semiconductor chip and partially sealing the leads and the first and second heat radiating members.Type: GrantFiled: June 20, 1996Date of Patent: December 30, 1997Assignee: Fujitsu LimitedInventors: Michio Sono, Kazuto Tsuji, Hideharu Sakoda, Yoshimi Suzuki, Masao Sakuma
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Patent number: 5684675Abstract: A semiconductor device unit includes a holder having a plurality of holding parts, and a plurality of semiconductor devices held by the holding parts of the holder. Each of the semiconductor devices has a generally parallelepiped shape with top and bottom surfaces and at least one side surface provided with leads which are exposed whereby the semiconductor device unit stands by itself on the leads.Type: GrantFiled: June 1, 1994Date of Patent: November 4, 1997Assignee: Fujitsu, Ltd.Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto
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Patent number: 5666064Abstract: A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: May 15, 1995Date of Patent: September 9, 1997Assignees: Fujitsu Limited, Kyushu Fujitsu Elecronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5656550Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.Type: GrantFiled: March 5, 1996Date of Patent: August 12, 1997Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki
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Patent number: 5654243Abstract: A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate of a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.Type: GrantFiled: August 14, 1996Date of Patent: August 5, 1997Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5637923Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: May 31, 1995Date of Patent: June 10, 1997Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma
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Patent number: 5625222Abstract: A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate at a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.Type: GrantFiled: July 27, 1994Date of Patent: April 29, 1997Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5574310Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.Type: GrantFiled: June 7, 1995Date of Patent: November 12, 1996Assignee: Fujitsu LimitedInventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
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Patent number: 5569625Abstract: A semiconductor process includes a stage, a semiconductor chip which is mounted on the stage, a plurality of electrode members which are wire bonded to the semiconductor chip, where a first gap is formed between the stage and one electrode member and a second gap is formed between two electrode members, a plurality of leads including inner leads which are wire bonded to at least one of the semiconductor chip and the electrode members and electrically connected thereto, and a resin package which encapsulates the semiconductor chip, the stage, the electrode members and the inner leads by a resin. The resin fills the first and second gaps, so that the stage and the one electrode member are isolated and the two electrode members are isolated.Type: GrantFiled: November 22, 1994Date of Patent: October 29, 1996Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Junichi Kasai, Hideharu Sakoda
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Patent number: 5521432Abstract: A semiconductor device includes a semiconductor chip, a die-pad on which the semiconductor chip is mounted, a package encapsulating the die pad and the semiconductor chip, and a plurality of leads electrically connected to the semiconductor chip and projecting from the package, wherein each of the leads has a lead body made of pure nickel (Ni) having a purity equal to or greater than 99% and a first film formed thereon, the first film being made of palladium (Pd).Type: GrantFiled: June 1, 1994Date of Patent: May 28, 1996Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Junichi Kasai, Michio Sono