Patents by Inventor Kazuto Tsuji

Kazuto Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5497032
    Abstract: A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: March 5, 1996
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5475259
    Abstract: A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: December 12, 1995
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation Limited
    Inventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
  • Patent number: 5451815
    Abstract: A semiconductor device includes vertical placement part for mounting the semiconductor device on a surface of a circuit board in a vertical position, and a connection part for making electrical connections between the circuit board and a semiconductor element. A stage is provided on which the semiconductor element is placed. The stage has supporting members causing the semiconductor device to vertically stand on the circuit board. Wiring boards, stacked on a side of the stage on which the semiconductor element is placed, have windows in which the semiconductor element is located. The vertical placement part includes wiring lines extending between edges of the wiring boards facing the circuit board and peripheries of the windows. The wiring lines have ends located in the vicinity of the edges of the wiring boards and have a shape enabling the semiconductor device to be mounted on the circuit board.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: September 19, 1995
    Assignee: Fujitsu Limited
    Inventors: Norio Taniguchi, Kazuto Tsuji, Junichi Kasai, Michio Sono
  • Patent number: 5440170
    Abstract: A semiconductor device employs a lead frame including a die pad (24) and a plurality of leads (25) provided outside the die pad, and is manufactured by sealing the die pad and its periphery by a resin after the die pad is fitted with the semiconductor chip (11). The die pad (24) is formed separately from the main part of the lead frame provided with leads, and is rounded at an entire outermost edge thereof and includes a flat plate shape. This die pad can be either formed rounded with ceramic or resin, or formed in metal and given a rounded edge through honing.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: August 8, 1995
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Junichi Kasai
  • Patent number: 5403776
    Abstract: A process of manufacturing semiconductor device accommodated in a package including a semiconductor chip, a package body for accommodating the semiconductor chip, and a plurality of terminal members embedded in the package body in electrical connection to the semiconductor chip and projecting from a bottom surface of the package body, wherein each of said terminal members is of spherical form, such that the terminal members roll substantially freely when placed on a flat surface, and of a substantially identical diameter.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Tetsuya Hiraoka, Tsuyoshi Aoki, Junichi Kasai
  • Patent number: 5399804
    Abstract: A semiconductor device includes a stage, a semiconductor chip which is mounted on the stage, a plurality of electrode members which are wire bonded to the semiconductor chip, where a first gap is formed between the stage and one electrode member and a second gap is formed between two electrode members, a plurality of leads including inner leads which are wire bonded to at least one of the semiconductor chip and the electrode members and electrically connected thereto, and a resin package which encapsulates the semiconductor chip, the stage, the electrode members and the inner leads by a resin. The resin fills the first and second gaps, so that the stage and the one electrode member are isolated and the two electrode members are isolated.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: March 21, 1995
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Kazuto Tsuji, Junichi Kasai, Hideharu Sakoda
  • Patent number: 5293064
    Abstract: A lead frame for manufacturing a semiconductor device has at least one set of substantially parallel leads having inner ends for connection to a semiconductor chip, outer ends for external connection and central portions therebetween and an outer tiebar interconnecting the outer ends and having an elongated guide hole therein, the longer dimension of the guide hole being parallel to the leads. A lead bending die has a locating pin respectively corresponding to and received in sliding engagement in each guide hole. The die maintains a center portion of them lead frame in a first plane and, with each locating pin remaining in sliding engagement within the respective, elongated guide hole, bends the central portions of the leads thereby to dispose the respective outer ends of the leads in a second plane, displaced from the first plane. The outer tiebar and the sliding engagement of the locating pin in the guide hole serve to prevent undesirable deformation of the leads as a result of the bending operation.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: March 8, 1994
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Masanori Yoshimoto, Kazuto Tsuji, Masao Sakuma, Kouichi Takeshita
  • Patent number: 5293072
    Abstract: A semiconductor device accommodated in a package includes a semiconductor chip, a package body for accommodating the semiconductor chip, and a plurality of terminal members embedded in the package body in electrical connection to the semiconductor chip and projecting from a bottom surface of the package body, wherein each of said terminal members is of spherical form, and of a substantially identical diameter.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: March 8, 1994
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Tetsuya Hiraoka, Tsuyoshi Aoki, Junichi Kasai
  • Patent number: 4724280
    Abstract: PLCC (Plastic Leaded Chip Carrier) for a LSI having protuberances on the bottom along its lateral side, is provided with interconnectors between leg portions of adjacent protuberances. Each interconnector is a swelling from the bottom surface of the main body of PLCC to fill the gap, i.e. a channel, between the protuberances. The height of the filling, namely the height of the interconnector, is lower than that of prior art protuberance to leave some space. This space, a channel, serves as a duct for solvent to flow therein smoothly to and from the narrow gap between the soldered lead and the top of the protuberance and is located adjoining this narrow gap. Therefore, the undesirably remaining flux in this narrow gap is perfectly removed by this smooth flow of the solvent. The leg portion of the protuberance is strengthened by the interconnector so that the occurrence of a crack of the protuberance when the moled PLCC is ejected from the molding cavities is considerably reduced.
    Type: Grant
    Filed: August 7, 1986
    Date of Patent: February 9, 1988
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Tsuyoshi Aoki, Michio Ono, Rikio Sugiura