Patents by Inventor Kazuya Fukuhara

Kazuya Fukuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8440376
    Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
  • Patent number: 8419950
    Abstract: According to one embodiment, a pattern forming method is disclosed. The method includes contacting a template with light curable resin on a substrate. The template comprises a concave-convex pattern including concave portions and convex portions, and a metal layer provided on a convex portion of the concave-convex pattern. The concave-convex pattern is to be contacted with the light curable resin. The pattern forming method further includes irradiating the light curable resin with light of a predetermined wavelength under a condition ?1=?2?2. Where ?1 is a complex relative permittivity of the metal layer corresponding to the predetermined wavelength, ?2 is a complex relative permittivity of the light curable resin corresponding to the predetermined wavelength.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kashiwagi, Kazuya Fukuhara
  • Patent number: 8407628
    Abstract: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamitsu Itoh, Takashi Hirano, Kazuya Fukuhara
  • Patent number: 8384229
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuya Fukuhara, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Patent number: 8373258
    Abstract: An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN.
    Type: Grant
    Filed: May 28, 2011
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Mizusaki, Kazuya Fukuhara
  • Publication number: 20130020741
    Abstract: According to one embodiment, an imprint method comprises coating a photo-curable organic material on a film to be processed, bringing a concave-convex pattern of a template into contact with the photo-curable organic material, applying a force to the template in such a state that the template is brought into contact with the photo-curable organic material, curing the photo-curable organic material by irradiating light onto the photo-curable organic material, in such a state that the template is brought into contact with the photo-curable organic material, and releasing the template from the photo-curable organic material after the light irradiation. The force applied to the template corresponds to a gap between a surface of the film to be processed and the template.
    Type: Application
    Filed: June 21, 2012
    Publication date: January 24, 2013
    Inventors: Masato SUZUKI, Takuya Kono, Manabu Takakuwa, Kazuya Fukuhara
  • Patent number: 8343692
    Abstract: According to one embodiment, an exposure apparatus inspection mask includes a substrate and a first pattern portion. The substrate has a major surface reflective to exposure light. The first pattern portion is provided on the major surface. The first pattern portion includes a first lower layer and a plurality of first reflection layers. The first lower layer is provided on the major surface and includes a plurality of first absorption layers periodically arranged at a prescribed pitch along a first direction parallel to the major surface and is absorptive to the exposure light. The plurality of first reflection layers are provided on a side of the first lower layer opposite to the substrate, are periodically arranged at the pitch along the first direction, expose at least part of each of the plurality of first absorption layers, and have higher reflectance for the exposure light than the first absorption layers.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: January 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Komine, Kazuya Fukuhara
  • Publication number: 20120328992
    Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Inventors: Kazuya Fukuhara, Takaki Hashimoto, Kazuyuki Masukawa, Yasunobu Kai
  • Patent number: 8293456
    Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Takaki Hashimoto, Kazuyuki Masukawa, Yasunobu Kai
  • Patent number: 8294889
    Abstract: A method for inspecting a nano-imprint template, includes irradiating light onto a template for nano-imprinting from a back surface side of the template, the template having a front surface where a pattern is formed, detecting near-field light which is generated near the front surface of the template by the irradiation of the light, and performing an inspection of the template on the basis of the detected near-field light.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kashiwagi, Kazuya Fukuhara
  • Publication number: 20120206702
    Abstract: Certain embodiments provide a computer-readable recording medium recording an exposing condition determination program. The program allows a computer to perform: a first step of dividing an illumination pupil into a plurality of regions; a second step of calculating, for each region, an imaging performance response indicative of relation between a brightness change from a first illumination shape and a change in an imaging performance evaluation amount for a transfer pattern; a third step of finding a brightness change amount for each region so that the imaging performance evaluation amount is maintained in a specified range; a fourth step of adding the brightness change amount to the first illumination shape to find a second illumination shape; and a step of performing the first to the fourth steps multiple times while changing a calculation condition parameter to find a second illumination shape as an illumination shape supplied to the exposure apparatus.
    Type: Application
    Filed: September 9, 2011
    Publication date: August 16, 2012
    Inventor: Kazuya FUKUHARA
  • Publication number: 20120163699
    Abstract: According to one embodiment, a mask determination method includes at least one of the in-plane error average value and the distribution of in-plane dispersions in a mask plane are measured with respect to at least one of the dimension and the optical characteristics of a mask pattern formed on a mask. Then, an illumination condition, under which a cost function representing an image performance formed on a substrate approaches a desired value when the exposure light is irradiated onto the mask and an on-substrate pattern is formed, is calculated based on at least one of the measured values. Further, whether the mask is acceptable or defective is determined based on the image performance when the on-substrate pattern is formed under the illumination condition.
    Type: Application
    Filed: September 13, 2011
    Publication date: June 28, 2012
    Inventor: Kazuya FUKUHARA
  • Patent number: 8142960
    Abstract: An exposure method has irradiating a mask with light based on an exposure performing condition, a first mask pattern and a second mask pattern being formed in the mask, and projecting images of the first mask pattern and second mask pattern onto a wafer through a projection lens, a lower-layer film material and a photoresist being sequentially laminated on the wafer, wherein the exposure performing condition is a condition on which, when exposure is performed on a predetermined exposure condition, the predetermined exposure condition is adjusted such that a difference between a wafer position at which a best focus is obtained for the image of the first mask pattern and a wafer position at which a best focus is obtained for the image of the second mask pattern falls within a predetermined range, the wafer position of the first mask pattern and the wafer position of the second mask pattern being predicted using film thicknesses and optical characteristics of the photoresist and the lower-layer film material.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: March 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Nagai, Kazuya Fukuhara
  • Publication number: 20120070985
    Abstract: According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 22, 2012
    Inventors: Takaki Hashimoto, Kazuya Fukuhara, Toshiya Kotani, Yasunobu Kai
  • Patent number: 8122385
    Abstract: In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Tatsuhiko Higashiki, Toshiya Kotani, Satoshi Tanaka, Takashi Sato, Akiko Mimotogi, Masaki Satake
  • Patent number: 8097942
    Abstract: A semiconductor device and a manufacturing method therefor wherein a wire for coupling an inner lead and a semiconductor chip with each other can be prevented from being electrically short-circuited to any other conductive part are provided. An inner lead portion has a tip arranged outside the outer circumferential end of the semiconductor chip as viewed on a plane. A power supply bar has a jutted portion extended between the outer circumferential end of the semiconductor chip and the tip of the inner lead portion as viewed on a plane. The upper face of the jutted portion is in a position lower than the upper face of the tip of the inner lead portion. A bonding wire for electrically coupling the semiconductor chip and the inner lead portion with each other has a bent portion outside the outer circumferential end of the semiconductor chip as viewed on a plane.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: January 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Misumi, Katsuyuki Fukudome, Kazushi Hatauchi, Kazuya Fukuhara, Kunihiro Yamashita
  • Patent number: 8085393
    Abstract: A mask pattern includes a first pattern having a line-and-space pattern extending in a first direction, a second pattern formed as a line-and-space pattern having a larger period than the first pattern and extending in the first direction, a third pattern having a line-and-space pattern extending in a second direction, and a fourth pattern formed as a line-and-space pattern having a larger period than the third pattern and extending in the second direction. Illumination light is obliquely incident on the first pattern and the second pattern from a first oblique direction, illumination light is obliquely incident on the third pattern and the fourth pattern from a second oblique direction, and a relative distance from the first pattern to the second pattern transferred on to an image receptor and a relative distance from the third pattern to the fourth pattern transferred onto the image receptor are measured and an optical characteristic of an exposure apparatus is ascertained based on the relative distances.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Kasa, Takashi Sato, Kazuya Fukuhara
  • Patent number: 8077292
    Abstract: A projection exposure method that projects the shape of a hole onto a wafer by projecting a diffracted light, which is produced by applying light to a mask having a pattern for forming a hole pattern, onto the wafer through a projection optical system for exposure, wherein, in a plane substantially perpendicular to an optical axis, the light applied to the mask has a first intensity distribution in which the intensity is higher in the vicinity of eight apexes of an octagon centered at the optical axis than in other areas, the mask has a plurality of first opening patterns are arranged in a rectangular lattice configuration having sides parallel to diagonals of the octagon passing through the optical axis, and a plurality of second opening patterns are arranged in a face-centered rectangular lattice configuration having sides parallel to diagonals of the octagon passing through the optical axis.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kitamura, Masaki Satake, Shoji Mimotogi, Kazuya Fukuhara
  • Publication number: 20110300472
    Abstract: According to one embodiment, an exposure apparatus inspection mask includes a substrate and a first pattern portion. The substrate has a major surface reflective to exposure light. The first pattern portion is provided on the major surface. The first pattern portion includes a first lower layer and a plurality of first reflection layers. The first lower layer is provided on the major surface and includes a plurality of first absorption layers periodically arranged at a prescribed pitch along a first direction parallel to the major surface and is absorptive to the exposure light. The plurality of first reflection layers are provided on a side of the first lower layer opposite to the substrate, are periodically arranged at the pitch along the first direction, expose at least part of each of the plurality of first absorption layers, and have higher reflectance for the exposure light than the first absorption layers.
    Type: Application
    Filed: September 20, 2010
    Publication date: December 8, 2011
    Inventors: Nobuhiro KOMINE, Kazuya Fukuhara
  • Publication number: 20110298116
    Abstract: An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN.
    Type: Application
    Filed: May 28, 2011
    Publication date: December 8, 2011
    Inventors: Shinya MIZUSAKI, Kazuya Fukuhara