Patents by Inventor Kazuyoshi Furukawa

Kazuyoshi Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220269750
    Abstract: An information processing device of solving of a shortest vector problem using an annealing computer that performs a single-spin flip, the information processing device including: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: dividing the shortest vector problem including a basis vector into a predetermined number of ranges, the basis vector being a multidimensional integer vector; generating, for each of the predetermined number of ranges, a specific term that causes a transition of a linear sum of specific variables among respective variables included in the basis vector; and generating, for each of the predetermined number of ranges, a Hamiltonian of a pseudo-multi-spin flip in which the specific term is added to the Hamiltonian of the single-spin flip.
    Type: Application
    Filed: November 29, 2021
    Publication date: August 25, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Jumpei YAMAGUCHI, Kazuyoshi FURUKAWA
  • Patent number: 10872147
    Abstract: A software detection device, the device including a memory and a processor coupled to the memory and the processor configured to execute a process, the process including generating at least one notification in response to at least one countermeasure process applied to a program to address a vulnerability to a software attack, each of the at least one notification including a countermeasure identifier to identify a countermeasure process performed, monitoring the at least one generated notification, and determining presence of the software attack based on the monitoring.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: December 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kazuyoshi Furukawa, Masahiko Takenaka, Hirotaka Kokubo
  • Patent number: 10819614
    Abstract: There is provided a network monitoring apparatus including a memory in which information of a remote operation and a combination of one or more command codes are associated with each other, and a processor coupled to the memory and the processor configured to acquire a command code of the one or more commands codes from a header of an encrypted execution request packet for executing the one or more commands for implementing a remote operation, determine whether or not there exists the combination included in a command code list in which acquired command codes are sequentially indicated, by referring the memory, and determine that the remote operation associated with the combination is successful when it is determined that there exists the combination included in the command code list.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 27, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuki Fujishima, Masanobu Morinaga, Kazuyoshi Furukawa
  • Patent number: 10348743
    Abstract: A method includes executing a determination process that determines that a setting value is a search key, the setting value being for an item from among a plurality of items in a record identified in a plurality of records, the plurality of records relating to a plurality of pieces of log information that are collected from a plurality of computers; executing a first identification process that identifies, as the record, another record including the search key from among the plurality of records; executing a second identification process that identifies, as the item, a new item from among the plurality of items, the new item being different from an item used to identify the another record in the executing of the first identification process; repeating executing of the processes; and outputting information on at least one computer that is suspected of a cyber-attack, based on the identified records.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Mebae Yamaoka, Takanori Oikawa, Kazuyoshi Furukawa, Masahiko Takenaka, Yuki Fujishima, Masanobu Morinaga
  • Patent number: 10339314
    Abstract: A device includes: a memory configured to store in advance a command transmitted from malware to hardware via an operating system; and a processor coupled to the memory and configured to: hook a first command transmitted from the operating system to the hardware, and transmit information that causes the malware to determine to terminate operation of the malware to the operating system when the hooked first command corresponds with the command stored in the memory.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 2, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Takanori Oikawa, Kazuyoshi Furukawa, Hirotaka Kokubo, Mebae Yamaoka, Masahiko Takenaka
  • Publication number: 20190149448
    Abstract: There is provided a network monitoring apparatus including a memory in which information of a remote operation and a combination of one or more command codes are associated with each other, and a processor coupled to the memory and the processor configured to acquire a command code of the one or more commands codes from a header of an encrypted execution request packet for executing the one or more commands for implementing a remote operation, determine whether or not there exists the combination included in a command code list in which acquired command codes are sequentially indicated, by referring the memory, and determine that the remote operation associated with the combination is successful when it is determined that there exists the combination included in the command code list.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 16, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuki Fujishima, Masanobu Morinaga, Kazuyoshi Furukawa
  • Publication number: 20180150633
    Abstract: A software detection device, the device including a memory and a processor coupled to the memory and the processor configured to execute a process, the process including generating at least one notification in response to at least one countermeasure process applied to a program to address a vulnerability to a software attack, each of the at least one notification including a countermeasure identifier to identify a countermeasure process performed, monitoring the at least one generated notification, and determining presence of the software attack based on the monitoring.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 31, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kazuyoshi Furukawa, Masahiko TAKENAKA, Hirotaka KOKUBO
  • Publication number: 20180068120
    Abstract: A method for malware detection includes: executing transmission processing that includes adding information pertaining to a specific file to a file list obtained from a storage device upon receiving a transmission command for the file list from an application, and transmitting, to the application, the file list to which the information pertaining to the specific file has been added; and executing determination processing that includes determining that the application is malware upon receiving an operating command pertaining to the specific file from the application.
    Type: Application
    Filed: August 16, 2017
    Publication date: March 8, 2018
    Applicant: Fujitsu Limited
    Inventors: Hirotaka Kokubo, Kazuyoshi Furukawa, Masahiko Takenaka
  • Publication number: 20170331857
    Abstract: A non-transitory recording medium storing a data protection program causing a computer to perform a process, the process includes: storing, in a memory, a first command to be transmitted from a malware to an operating system; hooking a second command that has been transmitted from an application to the operating system; determining whether the second command is stored in the memory; and switching a destination of writing data by the operating system from a first hardware to a second hardware when the second command is stored in the memory.
    Type: Application
    Filed: February 9, 2017
    Publication date: November 16, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kazuyoshi Furukawa, Hirotaka KOKUBO, TAKANORI OIKAWA, Masahiko TAKENAKA
  • Publication number: 20170302682
    Abstract: A device for analyzing malware includes a memory and a processor coupled to the memory. The memory is configured to store therein an instruction assumed to be transmitted to an operating system from malware. The processor is configured to hook a first instruction transmitted to the operating system from an application. The processor is configured to determine whether the first instruction is stored in the memory. The processor is configured to copy data stored in first hardware to second hardware different from the first hardware upon determining that the first instruction is stored in the memory. The first hardware is accessed by the operating system.
    Type: Application
    Filed: February 14, 2017
    Publication date: October 19, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hirotaka KOKUBO, Masahiko TAKENAKA, Kazuyoshi Furukawa, TAKANORI OIKAWA
  • Patent number: 9772819
    Abstract: An apparatus for generating physical random numbers includes a physical random number generator configured to generate physical random numbers, a test unit configured to perform a test process to check randomness of the physical random numbers, a minimum entropy estimating unit configured to estimate a minimum entropy based on statistical information generated as a byproduct of the test process, an entropy compressing unit configured to perform an entropy compression process using the physical random numbers as an input, and an entropy control unit configured to control based on the minimum entropy a number of bits of the physical random numbers input into the entropy compression process performed by the entropy compressing unit.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: September 26, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kazuyoshi Furukawa, Tetsuya Izu
  • Publication number: 20170099317
    Abstract: A communication device includes a memory configured to store information that defines permission and prohibition of access to another communication device from the communication device, and a processor coupled to the memory and configured to in a state where the information is not referenced by an operating system (OS), run the OS, when an access request to the another communication device is received from an application, based on the information, perform a determination of permission or prohibition of access to the another communication device, and based on a result of the determination, perform accessing to the another communication device or rejecting the access request.
    Type: Application
    Filed: September 20, 2016
    Publication date: April 6, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hirotaka KOKUBO, Kazuyoshi Furukawa, Masahiko TAKENAKA, Mebae Yamaoka, TAKANORI OIKAWA
  • Publication number: 20170083706
    Abstract: A device includes: a memory configured to store in advance a command transmitted from malware to hardware via an operating system; and a processor coupled to the memory and configured to: hook a first command transmitted from the operating system to the hardware, and transmit information that causes the malware to determine to terminate operation of the malware to the operating system when the hooked first command corresponds with the command stored in the memory.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 23, 2017
    Inventors: Takanori OIKAWA, Kazuyoshi Furukawa, Hirotaka Kokubo, Mebae Yamaoka, Masahiko Takenaka
  • Publication number: 20170070515
    Abstract: A method includes executing a determination process that determines that a setting value is a search key, the setting value being for an item from among a plurality of items in a record identified in a plurality of records, the plurality of records relating to a plurality of pieces of log information that are collected from a plurality of computers; executing a first identification process that identifies, as the record, another record including the search key from among the plurality of records; executing a second identification process that identifies, as the item, a new item from among the plurality of items, the new item being different from an item used to identify the another record in the executing of the first identification process; repeating executing of the processes; and outputting information on at least one computer that is suspected of a cyber-attack, based on the identified records.
    Type: Application
    Filed: June 27, 2016
    Publication date: March 9, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Mebae YAMAOKA, Takanori Oikawa, Kazuyoshi Furukawa, Masahiko Takenaka, Yuki Fujishima, Masanobu Morinaga
  • Patent number: 9510216
    Abstract: A node device includes: a processor configured to: receive a first packet that is transferred from a source to a destination via at least one node device including the node device, the first packet including a counter value regarding a number of transfers of the first packet, and first coding information according to a first key information and contents of the first packet, determine whether to conduct a verifying process on the first packet based on the counter value, verify the first coding information is same as a second coding information, the second coding information being generated according to the contents of the first packet and a second key information stored in the memory, change the counter value in the first packet to an initial value, and transmit the first packet including a changed counter value to the destination or any one of the plurality of node devices.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Yumi Sakemi, Kazuyoshi Furukawa, Hisashi Kojima, Masahiko Takenaka
  • Publication number: 20160171213
    Abstract: An apparatus stores first instructions including a call instruction and second instructions including a return instruction. When executing the second instructions called by the call instruction from the first instructions, the apparatus determines whether an instruction at a return address for return to the first instructions caused by the return instruction of the second instructions includes identification information. The apparatus continues processing of the first instructions when the instruction at the return address includes the identification information, and stops execution of the first instructions when the instruction at the return address does not include the identification information.
    Type: Application
    Filed: October 13, 2015
    Publication date: June 16, 2016
    Inventors: Kazuyoshi FURUKAWA, Hisashi Kojima, Masahiko TAKENAKA
  • Patent number: 9330270
    Abstract: An encryption processing device includes a memory configured to store a common key, and a processor configured to generate a random number which is an integer, to perform a bit transposition on the common key, the bit transposition being determined at least by the random number, to transmit the random number to another encryption processing device and to receive a response from the other encryption processing device, the response obtained by encryption using a common key stored in the other encryption processing device and a second randomized key generated by performing the bit transposition determined by the random number; and to authenticate the other encryption processing device either by comparing the response with the random number by decrypting the response with the common key, or by comparing the random number with the response by encrypting the random number with the common key.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 3, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takao Ochiai, Kouichi Itoh, Dai Yamamoto, Kazuyoshi Furukawa, Masahiko Takenaka
  • Publication number: 20160110165
    Abstract: A quality detecting method, includes: storing, in a memory, an upper limit value and a lower limit value that specify a distribution range of a score corresponding to at least one type for each of variant random number sequences generated by shuffling an initial random number sequence; and causing a computer to: generate verification random number sequences; calculate a score corresponding to the type for each of the verification random number sequences; compare the scores of the verification random number sequences with the upper limit value and the lower limit value; acquire a frequency at which the scores of the verification random number sequences are distributed in the distribution range based on a comparison result; and detect, based on the frequency, quality of a physical random number generation circuit.
    Type: Application
    Filed: September 8, 2015
    Publication date: April 21, 2016
    Inventors: Hirotaka KOKUBO, Dai YAMAMOTO, Masahiko TAKENAKA, Kazuyoshi Furukawa
  • Patent number: 9318664
    Abstract: According to one embodiment, a semiconductor light emitting element includes: a support substrate; a bonding layer provided on the support substrate; an LED layer provided on the bonding layer; and a buffer layer softer than the bonding layer. The buffer layer is placed in one of between the support substrate and the bonding layer and between the bonding layer and the LED layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Nunotani, Yasuhiko Akaike, Yoshinori Natsume, Kazuyoshi Furukawa
  • Patent number: 9319923
    Abstract: A node in an ad-hoc network includes a memory unit storing a concatenated counter value including an erasure counter value and a transmission counter value for the node; and a processor configured to: add one to the transmission counter value, when the node transmits data to another node in the ad-hoc network; transmit to the other node, the data and the updated concatenated counter value; detect erasure of the concatenated counter value in the memory unit; distribute in the ad-hoc network and upon detecting the erasure, an acquisition request for the erasure counter value; receive the erasure counter value consequent to the acquisition request; generate the concatenated counter value to include the received erasure counter value plus one and the transmission counter value after the erasure and indicating the number of transmissions as zero due to the erasure; and archive to the memory unit, the generated concatenated counter value.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka, Hisashi Kojima, Kazuyoshi Furukawa