Abstract: In a semiconductor memory device, a capacitor with a trench having a laterally expanded bottom part is provided, the area above the laterally expanded part being provided for a transistor and cell separation, this resulting in an increase in the degree of integration. This laterally expanded part is formed by etching a silicon oxide film which is sandwiched between a substrate and a silicon layer, and is obtained by forming a depression in a semiconductor substrate beforehand. A silicon layer or another semiconductor substrate is laminated by bonding to a semiconductor substrate such as this into which is formed a depression, a trench which extends to this depression being formed, and the required films being formed to obtain the desired trench capacitor. By forming an oxide film on all of or the depression part of the semiconductor substrate into which is formed the depression, it is possible to eliminate the influence of radiation, by improving insulation properties.

Abstract: The disclosed semiconductor liquid phase epitaxial growth method and apparatus and the wafer holder used therefor can improve the deposition of polycrystal, the non-uniformity of film thickness, the thermal deterioration of the substrate, etc. The wafer holder comprises a holder body (11) formed with at least one wafer accommodating space in which at least two semiconductor wafers (15) can be held in such a way that reverse surfaces of the two wafers are brought into contact with two opposing inner side walls of the wafer holder and right surfaces of the two wafers are opposed to each other with a predetermined space between the two; and a holder cover (12) for covering an open surface of the holder body (11). Further, the holder body (11) is formed with an inlet port (16) for injecting a source into the wafer accommodating space and an outlet port (13) for exhausting the source from the wafer accommodating space.

Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semicondcutor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

Abstract: A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: In a semiconductor sensor, the surfaces of first and second semiconductor substractes of a first conductivity type are made into flat surfaces by polishing the surfaces and are contacted each other so that the both substrates are bonded together. Source and claim regions are formed by diffusing an impurity of second conductivity type. The source and claim regions are separated through a through hole formed in the second substrate and are extended along the surface of the second substrate. An insulative layer is formed on the opposite surface of the second substrate and an inner surface of the through hole.

Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.

Abstract: A glass composition for covering a semiconductor element. The glass composition has excellent resistance to chemicals and excellent electric characteristics. The glass composition includes 3 to 8% by weight of Al.sub.2 O.sub.3, 35 to 45% by weight of SiO.sub.2, 10 to 30% by weight of ZnO, 5 to 30% by weight of PbO, 1 to 10% by weight of B.sub.2 O.sub.3, and more than 5% but not exceeding 20% by weight of an alkaline earth metal oxide selected from the group consisting of MgO, CaO, SrO and BaO, where the maximum contents of MgO, CaO, SrO and BaO are 7% by weight, 3% by weight, 7% by weight, and 15% by weight, respectively.