Patents by Inventor Kazuyuki Higashi

Kazuyuki Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343263
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10748928
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20200111810
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10553612
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20190326322
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
  • Patent number: 10381374
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20190088676
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
  • Publication number: 20190088618
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region.
    Type: Application
    Filed: February 26, 2018
    Publication date: March 21, 2019
    Inventors: Kazumichi TSUMURA, Kazuyuki HIGASHI
  • Patent number: 10083893
    Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: September 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Ogiso, Kazuyuki Higashi, Tatsuo Migita
  • Publication number: 20180261623
    Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.
    Type: Application
    Filed: August 28, 2017
    Publication date: September 13, 2018
    Inventors: Kazuyuki HIGASHI, Kazumichi TSUMURA, Ryota KATSUMATA, Fumitaka ARAI
  • Patent number: 10074667
    Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuyuki Higashi, Kazumichi Tsumura, Ryota Katsumata, Fumitaka Arai
  • Patent number: 10068775
    Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mika Fujii, Kazuyuki Higashi, Kazumichi Tsumura, Takashi Shirono
  • Patent number: 10026715
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ippei Kume, Kazuyuki Higashi
  • Patent number: 9669720
    Abstract: A V2X system includes an electrical power distribution system configured to draw electrical power from a grid, support the supply of the drawn electrical power to one or more primary electrical systems and support the exchange of electrical power with a battery bank including at least one rechargeable vehicle battery. A controller manages the exchange of electrical power between the electrical power distribution system and the battery bank by identifying a change rate in electrical power drawn by the electrical power distribution system from the grid, selecting an amount of electrical power for the electrical power distribution system to exchange with the battery bank based on the change rate, and signaling for the exchange of the selected amount of electrical power.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 6, 2017
    Assignee: Nissan North America, Inc.
    Inventors: Kazuyuki Higashi, Yukinari Kato
  • Patent number: 9630511
    Abstract: A vehicle-to-grid system connected to a power grid includes a first vehicle group of one or more vehicles connected to the power grid, a second vehicle group of one or more vehicles connected to the power grid, and a vehicle-to-grid controller. The vehicle-to-grid controller causes each vehicle from the second vehicle group to supply electrical power to the power grid at a nominal frequency and at an adjusted amplitude, and causes each vehicle from the first vehicle group to supply electrical power to the power grid at an adjusted frequency that is different than the nominal frequency and at a nominal amplitude that is different than the adjusted amplitude.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 25, 2017
    Assignee: Nissan North America, Inc.
    Inventor: Kazuyuki Higashi
  • Publication number: 20170076969
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming an overhanging portion in a perimeter region of a front surface side of a wafer provided with a semiconductor element on the front surface thereof by removing a portion of the wafer in perimeter region of the wafer from the front surface side of the wafer, bonding the front surface of the wafer to a supporting substrate, and thinning the wafer to less than 200 ?m in thickness by grinding the wafer from a rear surface side thereof.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 16, 2017
    Inventors: Takashi SHIRONO, Mika FUJII, Kazuyuki HIGASHI
  • Publication number: 20170069503
    Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 9, 2017
    Inventors: Mika FUJII, Kazuyuki HIGASHI, Kazumichi TSUMURA, Takashi SHIRONO
  • Publication number: 20160280090
    Abstract: A V2X system includes an electrical power distribution system configured to draw electrical power from a grid, support the supply of the drawn electrical power to one or more primary electrical systems and support the exchange of electrical power with a battery bank including at least one rechargeable vehicle battery. A controller manages the exchange of electrical power between the electrical power distribution system and the battery bank by identifying a change rate in electrical power drawn by the electrical power distribution system from the grid, selecting an amount of electrical power for the electrical power distribution system to exchange with the battery bank based on the change rate, and signaling for the exchange of the selected amount of electrical power.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: KAZUYUKI HIGASHI, YUKINARI KATO
  • Publication number: 20160280091
    Abstract: A V2X system includes an electrical power distribution system configured to draw electrical power from a grid, support the supply of the drawn electrical power to one or more primary electrical systems and support the exchange of electrical power with a battery bank including at least one rechargeable vehicle battery. A controller manages the exchange of electrical power between the electrical power distribution system and the battery bank by identifying a change rate in electrical power drawn by the electrical power distribution system from the grid, identifying the battery bank's starting state of charge, selecting an amount of electrical power for the electrical power distribution system to exchange with the battery bank based on the change rate, the battery bank's starting state of charge and a desired ending state of charge for the battery bank, and signaling for the exchange of the selected amount of electrical power.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: YUKINARI KATO, KAZUYUKI HIGASHI
  • Publication number: 20160276313
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ippei KUME, Kazuyuki HIGASHI