Patents by Inventor Kazuyuki Higashi
Kazuyuki Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230345726Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: ApplicationFiled: June 22, 2023Publication date: October 26, 2023Applicant: KIOXIA CORPORATIONInventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
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Patent number: 11729973Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: GrantFiled: January 28, 2021Date of Patent: August 15, 2023Assignee: KIOXIA CORPORATIONInventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Patent number: 11721520Abstract: A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.Type: GrantFiled: January 21, 2022Date of Patent: August 8, 2023Assignee: NuFlare Technology, Inc.Inventors: Kei Obara, Kazuyuki Higashi, Miyoko Shimada, Yoshiaki Shimooka, Hitomi Yamaguchi, Yoshikuni Goshima, Hirofumi Morita, Hiroshi Matsumoto
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Publication number: 20220270850Abstract: A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.Type: ApplicationFiled: January 21, 2022Publication date: August 25, 2022Applicant: NuFlare Technology, Inc.Inventors: Kei OBARA, Kazuyuki HIGASHI, Miyoko SHIMADA, Yoshiaki SHIMOOKA, Hitomi YAMAGUCHI, Yoshikuni GOSHIMA, Hirofumi MORITA, Hiroshi MATSUMOTO
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Publication number: 20210151465Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
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Patent number: 10950630Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: GrantFiled: July 13, 2020Date of Patent: March 16, 2021Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Publication number: 20200343263Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Patent number: 10748928Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: GrantFiled: December 9, 2019Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Publication number: 20200111810Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Patent number: 10553612Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: GrantFiled: July 2, 2019Date of Patent: February 4, 2020Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Publication number: 20190326322Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
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Patent number: 10381374Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: GrantFiled: March 5, 2018Date of Patent: August 13, 2019Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
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Publication number: 20190088676Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.Type: ApplicationFiled: March 5, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
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Publication number: 20190088618Abstract: A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region.Type: ApplicationFiled: February 26, 2018Publication date: March 21, 2019Inventors: Kazumichi TSUMURA, Kazuyuki HIGASHI
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Patent number: 10083893Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.Type: GrantFiled: September 10, 2014Date of Patent: September 25, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koji Ogiso, Kazuyuki Higashi, Tatsuo Migita
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Publication number: 20180261623Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.Type: ApplicationFiled: August 28, 2017Publication date: September 13, 2018Inventors: Kazuyuki HIGASHI, Kazumichi TSUMURA, Ryota KATSUMATA, Fumitaka ARAI
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Patent number: 10074667Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.Type: GrantFiled: August 28, 2017Date of Patent: September 11, 2018Assignee: Toshiba Memory CorporationInventors: Kazuyuki Higashi, Kazumichi Tsumura, Ryota Katsumata, Fumitaka Arai
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Patent number: 10068775Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.Type: GrantFiled: August 10, 2016Date of Patent: September 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mika Fujii, Kazuyuki Higashi, Kazumichi Tsumura, Takashi Shirono
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Patent number: 10026715Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.Type: GrantFiled: March 9, 2016Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ippei Kume, Kazuyuki Higashi
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Patent number: 9669720Abstract: A V2X system includes an electrical power distribution system configured to draw electrical power from a grid, support the supply of the drawn electrical power to one or more primary electrical systems and support the exchange of electrical power with a battery bank including at least one rechargeable vehicle battery. A controller manages the exchange of electrical power between the electrical power distribution system and the battery bank by identifying a change rate in electrical power drawn by the electrical power distribution system from the grid, selecting an amount of electrical power for the electrical power distribution system to exchange with the battery bank based on the change rate, and signaling for the exchange of the selected amount of electrical power.Type: GrantFiled: March 27, 2015Date of Patent: June 6, 2017Assignee: Nissan North America, Inc.Inventors: Kazuyuki Higashi, Yukinari Kato