Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: The present invention provides a microgel having a mean particle size of 0.1-1,000 &mgr;m, the microgel being produced from a gel which is formed by use of a hydrophilic compound capable of forming a gel. An external composition containing the microgel provides an excellent sensation during use; i.e., the composition provides neither sticky sensation during use nor frictional sensation. Furthermore, even when a large amount of a pharmaceutical ingredient, such as a whitening ingredient, or a salt is incorporated into the composition, the viscosity of the composition is not lowered, and the composition exhibits excellent viscosity increasing property. In addition, the composition exhibits long-term stability, without inviting separation of water.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: A microcapsule of the present invention is characterized in that it encapsulate oil droplets having average particle size of 0.01 to 3 &mgr;m and its capsulating agent is a hydrophilic polymer gelling agent. The main component of the capsulating agent is preferably a hydrophilic polymer gelling agent which hardens by heating and cooling, and, in particular, agar or carrageenan. In the making method of the present invention, a microcapsule can be made efficiently due to no loss in the inner oil phase, and its particle size can easily be controlled. The microcapsule is excellent in shearing-resistance, store stability. Also, if the fracture strength of the microcapsule is within a specific range, a microcapsule which releasing characteristic of encapsulated oil droplets when applied is immediately-, gradually- or non-releasing can be obtained.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A copolymer having silyl groups with at least one reactive functional group bonded thereto. The copolymer comprises a monomer (A) shown by the following Formula (I): wherein R1 is hydrogen atom or methyl; R2 is alkylene group having 1-6 carbon atoms; and R3, R4 and R5 each is a reactive functional group which can cross-link molecules of the copolymer by hydrolyzing. Further, the copolymer preferably comprises, as a constituent monomer, an alkyl (meth)acrylate and a siloxane-containing (meth)acrylate. A coating-forming method comprises hydrolyzing the composition on a material to be treated to cross-link molecules of the copolymer when on the material. A coating of the cross-linked copolymer has resistance to washing. This coating can modify the nature of hair, improve make-up retention, and provide skin-protecting. It can impart water-repellency, resistance to fouling, suitability as a sizing and crease resistance to fibers.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: There is provided a .beta.-1,3 glucan obtained by applying ultrasonic treatment in a mixed solution of an organic solvent containing at least dimethyl sulfoxide to remove the contaminant proteins and there is provided a coupling medium for a probe of an ultrasonograph comprised of a gel composed of a .beta.-1,3 glucan, as a main component, from which contaminant proteins have been removed as a coupling medium for a probe of an ultrasonograph superior in physical properties and safety.

Abstract: A resin-encapsulated semiconductor package and a packaging structure, make it possible to provide for a high density mounting arrangement. Specifically, outer leads protrude from the two long sides of a rectangular package. The inner leads in the package, connected to the outer leads protruding from one long side, are connected through wires to the bonding pads of a semiconductor chip encapsulated in the package, whereas the inner leads in the package, connected to the outer leads protruding from the other long side, are in an electrically floating state in the package. The semiconductor packages are arranged in a direction on a card-shaped mounting board, and the opposed outer leads of adjoining semiconductor packages are electrically connected by wiring on the mounting board. The wirings are laid below the semiconductor packages so that they extend generally linearly.

Abstract: A phenylenediamine derivative or a salt thereof in accordance with the present invention is expressed by the following formula 1: ##STR1## wherein A represents a group expressed by --CO--, --CH.sub.2 CO--, --CS--, or --SO.sub.2 --; Y represents a carbon atom or nitrogen atom; R.sub.1 represents a lower alkyl group; R.sub.2 represents a hydrogen, lower alkyl, alkenyl, benzyl, or benzoyl group; and each of R.sub.3 and R.sub.4 represents an alkyl group having 1-10 carbon atoms. The phenylenediamine derivative above mentioned, as a radical scavenger, has antioxidant effect and lipid peroxidation inhibitory activity so as to be available for inhibiting brain infarction or brain edema.

Abstract: A semiconductor integrated circuit device includes in a P-type well region containing a memory substrate a array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage.