Patents by Inventor Kazuyuki Nakamura
Kazuyuki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140222653Abstract: The present invention applies a particle filter method to the PUCK model for calculating a true market price. First, a probability density function of a parameter is obtained by generating a group of particles having parameters representing the state of the PUCK model each having different values. Then, the degree of conformity of each of the particles is evaluated and the particles are resampled as follows in accordance with the degree of conformity. A random number is compared with a predetermined value, where particles are regenerated in accordance with probability density function such as a normal distribution for making a parameter value of the model at time (t) into a mean value when the random number is greater than the predetermined value, and where the particles are regenerated taking a uniform distribution as the probability density function when the random number is less than the predetermined value.Type: ApplicationFiled: September 7, 2012Publication date: August 7, 2014Applicant: Tokyo Institute of TechnologyInventors: Misako Takayasu, Yoshihiro Yura, Kazuyuki Nakamura
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Patent number: 8684841Abstract: A storage medium having stored thereon a game program executable by a computer 21 of a game apparatus 1 including touch coordinate pair input means for outputting coordinate information based on a predetermined coordinate system in accordance with a touch operation performed by a player. A first object P1 and a second object P2 are displayed on a display screen based on first object position data DC3 and second object position data DC5. While input coordinate pairs are being detected, the first object position data DC3 is updated based on the input coordinate pairs. The second object position data DC5 is updated based on the first object position data DC3.Type: GrantFiled: February 13, 2006Date of Patent: April 1, 2014Assignees: Nintendo Co., Ltd., Hal Laboratory Inc.Inventors: Hitoshi Kikkawa, Kazuyuki Nakamura, Katsuhiro Sakoda
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Patent number: 8492059Abstract: An electrophotographic photoreceptor, includes: a conductive support; and a photosensitive layer provided on or above the conductive support, the photosensitive layer including an outermost surface layer at the farthest location from the conductive support, wherein the outermost surface layer contains: coated insulating inorganic particles obtained by subjecting insulating inorganic particles having a specific surface area of not more than about 300 m2/g to a coating treatment with an aromatic functional group-containing compound; and fluorine-containing organic particles.Type: GrantFiled: October 20, 2009Date of Patent: July 23, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Shigeto Hashiba, Kazuhiro Koseki, Kaori Iemura, Kenta Ide, Satoya Sugiura, Fuyuki Kano, Kazuyuki Nakamura
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Patent number: 8263299Abstract: An electrophotographic photoreceptor comprises: an electroconductive support; and a photosensitive layer on the electroconductive support, wherein the photosensitive layer having a dynamic hardness of from 20×109 to 150×109 N/m2 and an elastic deformation ratio of from 15 to 80%.Type: GrantFiled: February 17, 2006Date of Patent: September 11, 2012Assignee: Fuji Xerox Co., Ltd.Inventors: Kaori Iemura, Katsumi Nukada, Hidemi Nukada, Kazuyuki Nakamura
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Patent number: 8169813Abstract: A method for evaluating an SRAM memory cell in which the time required for designing the SRAM memory cell can be shortened by evaluating static noise margin in a shortened time. A recording medium which records an evaluation program is also provided. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a first inverter of the SRAM memory cell, and the first proximity curve function is specified by fitting the input/output characteristic data of the first inverter to the proximity curve. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a second inverter of the SRAM memory cell, and the second proximity curve function is specified by fitting the input/output characteristic data of the second inverter to the proximity curve.Type: GrantFiled: March 10, 2008Date of Patent: May 1, 2012Assignee: Kyushu Institute of TechnologyInventors: Kazuyuki Nakamura, Hiroki Koike
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Patent number: 8142969Abstract: An electrophotographic photoreceptor includes a conductive support; a photosensitive layer; and a surface protective layer as an outermost layer of the electrophotographic photoreceptor, wherein the electrophotographic photoreceptor satisfies following formulas (a) and (b): 3.6?(A+B)/C×100?6??(a) B?0.3??(b) wherein A (?m) represents a ten-point-averaged surface roughness RZJIS94 of the conductive support, B (?m) represents a ten-point-averaged surface roughness RZJIS94 of the surface protective layer, and C (%) represents a reflectivity of the surface protective layer against the conductive support.Type: GrantFiled: March 25, 2008Date of Patent: March 27, 2012Assignee: Fuji Xerox Co., Ltd.Inventors: Tetsuya Ezumi, Masayuki Nishikawa, Daisuke Haruyama, Hirofumi Nakamura, Kazuyuki Nakamura
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Patent number: 8118558Abstract: A camber line in a radial section of a runner vane has a curved part extending near the tip of the runner vane is convex toward the front surface of the runner vane. The runner vane is formed in a shape meeting a condition expressed by: ?s<?p, where ?s is the radius of curvature of the back surface of the runner vane and ?p is the radius of curvature of the front surface of the runner vane. The runner vane of this shape suppresses flows toward the tip thereof to moderate the variation of flow velocity in the turning direction. Consequently, loss can be reduced without impeding the recover of pressure in a draft tube.Type: GrantFiled: April 10, 2009Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Nakamura, Norio Ohtake, Sakito Anpuku
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Patent number: 7924636Abstract: To provide an electronic circuit device that can change a characteristic after package sealing and that achieves a reduction in miscellaneous tasks during characteristic setting. The electronic circuit device includes: a burst detecting circuit 7 for detecting, from an input and output terminal 4, a prescribed write activation burst having a length that is larger than or equal to a prescribed time; a signal-pattern detecting circuit 9 for putting a serial interface 8 into an input-enable state in which setting data can be input, when the write activation burst is detected; and a volatile memory 10 and a nonvolatile memory 11 for storing, in the input-enable state, a setting-data signal input from the input and output terminal 4. An operation state of a functional circuit 6 is set in accordance with the setting data written in the volatile memory 10 or the nonvolatile memory 11.Type: GrantFiled: January 29, 2008Date of Patent: April 12, 2011Assignee: Kyushu Institute of TechnologyInventors: Hiroyuki Morimoto, Kazuyuki Nakamura
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Publication number: 20100196810Abstract: An electrophotographic photoreceptor, includes: a conductive support; and a photosensitive layer provided on or above the conductive support, the photosensitive layer including an outermost surface layer at the farthest location from the conductive support, wherein the outermost surface layer contains: coated insulating inorganic particles obtained by subjecting insulating inorganic particles having a specific surface area of not more than about 300 m2/g to a coating treatment with an aromatic functional group-containing compound; and fluorine-containing organic particles.Type: ApplicationFiled: October 20, 2009Publication date: August 5, 2010Applicant: FUJI XEROX CO., LTD.Inventors: Shigeto HASHIBA, Kazuhiro KOSEKI, Kaori IEMURA, Kenta IDE, Satoya SUGIURA, Fuyuki KANO, Kazuyuki NAKAMURA
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Publication number: 20100115352Abstract: A method for evaluating an SRAM memory cell in which the time required for designing the SRAM memory cell can be shortened by evaluating static noise margin in a shortened time. A recording medium which records an evaluation program is also provided. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a first inverter of the SRAM memory cell, and the first proximity curve function is specified by fitting the input/output characteristic data of the first inverter to the proximity curve. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a second inverter of the SRAM memory cell, and the second proximity curve function is specified by fitting the input/output characteristic data of the second inverter to the proximity curve.Type: ApplicationFiled: March 10, 2008Publication date: May 6, 2010Applicant: Kyushu Institute of TechnologyInventor: Kazuyuki NAKAMURA
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Publication number: 20100086394Abstract: A hydraulic machine having a hydro turbine runner which has a crown at a center and a band along an outer periphery, and is formed around the axis of rotation, long blades which are arranged along the circumferential direction of the axis of rotation, and whose center-side ends are supported by the crown, and periphery-side ends are supported by the band, and short blades which are arranged between the long blades, and whose center-side ends are supported by the crown, periphery-side ends are supported by the band, and rear edges are curved in a rotation direction of the hydro turbine runner in turbine operation, on a plane of projection perpendicular to the axis of rotation.Type: ApplicationFiled: October 5, 2009Publication date: April 8, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuyuki Enomoto, Kazuyuki Nakamura, Takanori Nakamura, Akira Shinohara, Kotaro Tezuka
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Patent number: 7682134Abstract: A Francis pump-turbine includes a runner provided with runner blades arranged around in a circumferential direction of a main shaft of the runner, each of the runner blades being supported by a band at a bottom side thereof in a blade height direction and supported by a crown at a head side in the blade height direction, in which the runner blade is formed, at a trailing edge thereof, with a curved portion expanding to the main shaft when the turbine is in operation, the curved portion has a maximum point with respect to a straight line connecting a crown-side trailing edge connecting end at which the trailing edge and the crown are connected and a band-side trailing edge connecting end at which the trailing edge and the band are connected, and an angle ? formed by a straight line connecting the maximum point and the crown-side trailing edge connecting end and a straight line connecting the maximum point and the band-side trailing edge connecting end is set to be within a range of ??150°.Type: GrantFiled: October 11, 2006Date of Patent: March 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Nakamura, Kotaro Tezuka, Toshifumi Kurokawa
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Publication number: 20100020625Abstract: To provide an electronic circuit device that can change a characteristic after package sealing and that achieves a reduction in miscellaneous tasks during characteristic setting. The electronic circuit device includes: a burst detecting circuit 7 for detecting, from an input and output terminal 4, a prescribed write activation burst having a length that is larger than or equal to a prescribed time; a signal-pattern detecting circuit 9 for putting a serial interface 8 into an input-enable state in which setting data can be input, when the write activation burst is detected; and a volatile memory 10 and a nonvolatile memory 11 for storing, in the input-enable state, a setting-data signal input from the input and output terminal 4. An operation state of a functional circuit 6 is set in accordance with the setting data written in the volatile memory 10 or the nonvolatile memory 11.Type: ApplicationFiled: January 29, 2008Publication date: January 28, 2010Applicant: KYUSHU INSTITUTE OF TECHNOLOGYInventors: Hiroyuki Morimoto, Kazuyuki Nakamura
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Publication number: 20090257879Abstract: A camber line in a radial section of a runner vane has a curved part extending near the tip of the runner vane is convex toward the front surface of the runner vane. The runner vane is formed in a shape meeting a condition expressed by: ?s<?p, where ?s is the radius of curvature of the back surface of the runner vane and ?p is the radius of curvature of the front surface of the runner vane. The runner vane of this shape suppresses flows toward the tip thereof to moderate the variation of flow velocity in the turning direction. Consequently, loss can be reduced without impeding the recover of pressure in a draft tube.Type: ApplicationFiled: April 10, 2009Publication date: October 15, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuyuki Nakamura, Norio Ohtake, Sakito Anpuku
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Publication number: 20080273897Abstract: An electrophotographic photoreceptor includes a conductive support; a photosensitive layer; and a surface protective layer as an outermost layer of the electrophotographic photoreceptor, wherein the electrophotographic photoreceptor satisfies following formulas (a) and (b): 3.6?(A+B)/C×100?6 ??(a) B?0.3 ??(b) wherein A (?m) represents a ten-point-averaged surface roughness RZJIS94 of the conductive support, B (?m) represents a ten-point-averaged surface roughness RZJIS94 of the surface protective layer, and C (%) represents a reflectivity of the surface protective layer against the conductive support.Type: ApplicationFiled: March 25, 2008Publication date: November 6, 2008Applicant: FUJI XEROX CO., LTD.Inventors: Tetsuya Ezumi, Masayuki Nishikawa, Daisuke Haruyama, Hirofumi Nakamura, Kazuyuki Nakamura
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Patent number: 7438521Abstract: A stay ring of a hydraulic turbine has: a ring-shaped upper wall, a ring-shaped lower wall arranged below the upper wall forming a ring-shaped flow channel between the upper wall and the lower wall; and stay vanes arranged in array with spaces in a peripheral direction in the ring-shaped flow channel and rigidly secured to the upper and lower walls. The upper wall and the lower wall are inclined so as to reduce height of the ring-shaped flow channel toward outlet at least near inlet end thereof. The straightening bodies are arranged along inner surfaces of the upper wall and the lower wall at least near inlet end to reduce inclination of water flow in the stay ring.Type: GrantFiled: July 7, 2006Date of Patent: October 21, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Enomoto, Toshiaki Suzuki, Kazuyuki Nakamura, Taizo Inagaki
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Patent number: 7359238Abstract: A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit includes a first FET MNM1 forming a source-drain path between a ground potential GND and a bit line BL; a second FET MNM2 forming a source-drain path between the ground potential GND and a differential pair line BL_; a third FET MNM3 to open/close the connection between a drain terminal of the first FET MNM1 and the bit line BL; and a fourth FET MNM4 to open/close the connection between a drain terminal of the second FET MNM2 and the differential pair line BL_.Type: GrantFiled: March 30, 2005Date of Patent: April 15, 2008Assignee: Kitakyushu Foundation for the Advancement of Industry, Science and TechnologyInventor: Kazuyuki Nakamura
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Publication number: 20070274127Abstract: A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit includes a first FET MNM1 forming a source-drain path between a ground potential GND and a bit line BL; a second FET MNM2 forming a source-drain path between the ground potential GND and a differential pair line BL_; a third FET MNM3 to open/close the connection between a drain terminal of the first FET MNM1 and the bit line BL; and a fourth FET MNM4 to open/close the connection between a drain terminal of the second FET MNM2 and the differential pair line BL_.Type: ApplicationFiled: March 30, 2005Publication date: November 29, 2007Inventor: Kazuyuki Nakamura
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Patent number: 7248507Abstract: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.Type: GrantFiled: December 12, 2006Date of Patent: July 24, 2007Assignee: Nscore Inc.Inventor: Kazuyuki Nakamura
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Publication number: 20070140852Abstract: A Francis pump-turbine includes a runner provided with runner blades arranged around in a circumferential direction of a main shaft of the runner, each of the runner blades being supported by a band at a bottom side thereof in a blade height direction and supported by a crown at a head side in the blade height direction, in which the runner blade is formed, at a trailing edge thereof, with a curved portion expanding to the main shaft when the turbine is in operation, the curved portion has a maximum point with respect to a straight line connecting a crown-side trailing edge connecting end at which the trailing edge and the crown are connected and a band-side trailing edge connecting end at which the trailing edge and the band are connected, and an angle a formed by a straight line connecting the maximum point and the crown-side trailing edge connecting end and a straight line connecting the maximum point and the band-side trailing edge connecting end is set to be within a range of ??150°.Type: ApplicationFiled: October 11, 2006Publication date: June 21, 2007Inventors: Kazuyuki Nakamura, Kotaro Tezuka, Toshifumi Kurokawa