Abstract: The present invention provides a serial-parallel conversion apparatus comprises N conversion circuits, each having: a separator for dividing an input data from an upper node according to a clock signal from the upper node, into a plurality of data corresponding to a plurality of terminals; and a clock generator that divides by two the input clock signal and outputs a resultant clock as a clock signal to a lower node. These N conversion circuits are connected in a tree structure. Thus, each separator divides a data according to a clock supplied from an immediate upper node, and each clock generator divides by two the input clock signal. The resultant clock signal serves as a clock signal in a conversion circuit of a lower node. Accordingly, it is possible to minimize the signal line length for transmitting the clock signal. This enables to obtain an optimal clock signal timing.

Abstract: The present invention aims to present an electronic component which is free from the fear of sneaking-in of water etc. from the edge of electrode, by covering the electrode edge with resin. For the purpose, external electrodes (3) are formed at both ends of varistor (1) comprised of ceramic sheet (1a) and internal electrode (2) laminated alternately, and then, a within-the-surface insulation layer (30) is formed by covering the porous surface inside the varistor (1), or filling the Porosity, with silicone resin, and an outside-the-surface insulation layer (31) is formed covering the surface of varistor (1) and the edge of external electrode (3).

Abstract: Disclosed is an attachment mounting/demounting device for working machinery by which a pin of an attachment held in engagement with an engagement groove of the mounting/demounting device can be surely locked and operation for locking and unlocking the pin can be easily performed. The mounting/demounting device comprises a latch capable of switching over between a release posture allowing a first pin to come into and out of a first engagement groove and an engagement posture preventing slip-off of the pin fitted to the engagement groove, a lock piston capable of switching over between a lock posture locking the latch in the engagement posture and an unlock posture releasing the latch from the lock posture, and a biasing spring for always biasing the lock piston toward the lock posture.

Abstract: An interface circuit includes first transistors for driving bus lines through which data is transmitted between a plurality of semiconductor elements. The interface circuit controls the data transmitted through the bus lines when the first transistors are in the ON state. The interface circuit also includes second transistors which share a ground line with the first transistors and in which currents equivalent to currents flowing in the first transistors flow in the ON state. The second transistors are set in the ON state when the first transistors are set in the OFF state, and vice versa.

Abstract: A system and method for a generating a data stream for encoding by combining data from a multiple of sources. In order to maintain a continuous phase in the combined data stream, any phase differentials between the data supplied from the multiple sources are eliminated upon combination of the source data. The phase differential between the data from any two different sources is eliminated by trimming data from one of the sources such that when the trimmed data is combined with the data from the other source the resulting combined stream has a continuous phase.

Abstract: An electrophotographic photoreceptor excellent in wear resistance and low in residual potential comprising a conductive support, and a photoconductive layer and a protective layer formed on the conductive support. The protective layer contains a finely divided metal oxide powder and a binder resin composed of a polymer containing an acrylate or a methacrylate having at least one silicon-containing functional group as a monomer component, the polymer being crosslinked with said silicon-containing functional group. Also disclosed is an image forming method using the electrophotographic photoreceptor.

Abstract: A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, .phi.0 to .phi.8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, a timing generation proportional to the external clock cycle without being affected by a production process or the like to enable us to provide a flexible timing designing.

Abstract: To provide a bi-directional interface circuit which can reduce the simultaneous switching noise and the power consumption even at transitions of the signal direction, a bi-directional interface circuit of the invention comprises: an encoder (10) for generating an output bit sequence in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal and a redundant bit so that signal alteration rate of the output bit sequence to a preceding bit sequence thereof is less than a half; a decoder (20) for decoding the input bit sequence into an original bit sequence; and bypass lines (3) for bypassing the input bit sequence to the encoder for enabling the encoder to refer to the input bit sequence as the preceding bit sequence when the LSI chip begins to transfer the original signal.

Abstract: To judge whether or not the number of high-level bits among N (N.ltoreq.2) bits of an input signal is greater than a predetermined number M (1.ltoreq.M<N), a judging circuit has a differential amplifier, N primary MISFETs, M secondary MISFETs, and primary and secondary resistors having the same resistance. Sources of the primary MISFETs are connected to the ground in common. Drains of the primary MISFETs are connected to one end of the primary resistor in common. The other end of the primary resistor is supplied with a power-supply voltage. Gates of the primary MISFETs are supplied with the N bits, respectively. The primary MISFETs have on-currents, respectively, which are equal to one another. An inverted input terminal of the amplifier is connected to the above-mentioned one end of the primary resistor. Sources of the secondary MISFETs are connected to the ground in common. Drains of the secondary MISFETs are connected to one end of the-secondary resistor in common.

Abstract: A decoder circuitry is provided between input signal lines and word lines. The number of the word lines is larger than the input signal lines. The decoder circuitry comprises a plurality of stages including at least an input side stage adjacent to the input signal lines and an output side stage adjacent to the word lines. Each of the plurality of stages includes plural logic circuits. The plural stages so vary as not to decrease in the number of the logic circuits when the stage approaches to the word lines so that the number of the logic circuits in the input side stage adjacent to the input signal lines is smaller than the number of the logic circuits in the output side stage adjacent to the word lines. Each of the logic circuits has a plurality of field effect transistors.

Abstract: A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, .phi.0 to .phi.8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, timing generation proportional to the external clock cycle without being affected by a production process or the like provides a flexible timing design.

Abstract: In an electronic mail associated type computer system network equipped with a computer system for executing a job and a general-purpose electronic mail system, a user of an electronic mail can freely recognize a condition of an execution result of a job performed in the computer system and a job execution result. Also, these results are available from a desired output device for the user. When a mail processing unit employed in the computer system analyzes a mail statement about the job execution derived from the electronic mail system, and the job execution is completed, this mail processing unit sends to the electronic mail system, such a mail statement for the completion of the job execution containing information about fail/safe execution result. Upon receipt of this report, the user designates the output device into a response mail so as to output the job execution result from the designated output device.

Abstract: In an arrangement of a mail terminal 1, an electronic mail system 2, a job control terminal 4, and a computer system 3, a user makes a proposal of a file operation via a mail by way of the mail terminal 1. The electronic mail system 2 stores therein the proposal mail, exchanges this proposal mail with the job control terminal 4, and furthermore distributes a file operation result to the respective mail terminals. The job control terminal 4 receives a mail from the electronic mail system 2, and interprets the proposal mail, thereby executing a conversion from a mail ID into a host ID, a judgement of an access authorization with respect to the designated file, and a production of an instruction to the computer process system 3. Furthermore, an execution host computer is selected by monitoring operation conditions of the host computers.

Abstract: An electrophotographic photoreceptor comprising a conductive substrate having provided thereon a photosensitive layer, wherein said photosensitive layer contains, as charge transporting material (i) at least one triarylamine compound represented by formula (I) ##STR1## wherein the definition of Ar.sub.1, Ar.sub.2 are described in the present specification; and (ii) at least one benzidine compound represented by formula (II) ##STR2## wherein the definition of R.sub.1, R.sub.1 ', R.sub.2, R.sub.2 ', R.sub.3, R.sub.3 ', m and n is described in the specification. The photoreceptor maintains its electrical characteristics stably on repeated use.

Abstract: In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of static memory cells, at intersections between the word lines and the pairs of bit lines, and at least one sense amplifier for sensing a difference in potential between a selected pair of bit lines, a resistive load is connected to a substantial center location of each of the bit lines.

Abstract: A regulating system incorporated in a static type random access memory device store control data codes indicative of margins between actual circuit characteristics of a charging circuit and a sense amplifier and standard circuit characteristics thereof in a rewritable manner, and the control data codes are given to the regulating system through a testing operation before delivery from a factory for enhancing the device characteristics and the production yield.

Abstract: A method of reclaiming a plastic product having a paint film, including the steps of: obtaining crushed particles by crushing a plastic product having a paint film into particles of a predetermined size; supplying the crushed particles to a screw-type extruder; kneading and fusing the crushed particles while supplying water thereto; and obtaining a plastic by discharging a gas produced by decomposing the paint film and vaporized water.

Abstract: A job control terminal creates a unit configuration table indicating the configuration of units connected to each of a plurality of processors in a multi-processor system. The job control terminal also creates an operating state table indicating an operating state of each processor including a CPU using ratio, I/O using ratio, memory using ratio, response time, and so on. When the job control terminal receives electronic mail for requesting job execution from a user through an electronic mail terminal, the job control terminal selects a processor assigned to execute the requested job based on the unit configuration table and the operating state table. When it is determined from the states of the processors that the requested job cannot be executed, information indicating that the job is unacceptable is transmitted from the job control terminal to the electronic mail terminal.

Abstract: An electrophotographic photoreceptor comprising an electroconductive support having thereon a light-sensitive layer. At least the outermost layer of the light-sensitive layer contains (1) fine grains of at least one of a melamine-formaldehyde condensate and a benzoguanamine-formaldehyde condensate, and, as a binder resin, a polycarbonate resin comprising a constitutive unit represented by formula (II); or (2) fine grains of a benzoguanamine-melamine-formaldehyde condensate having an average grain size of from 0.03 to 4 .mu.m.

Abstract: A read circuit is comprised of a circuit for reading out a data signal from one selected among a plurality of arrayed semiconductor memory cells by using a cascode type sense amplifier, in which the drop of the power supply voltage level and the level shift of the bit lines are properly set to allow the cascode type sense amplifier to operate at a low voltage. The bit lines are clamped to a low voltage level obtained by lowering the power supply voltage level and then the voltage level of the bit lines is shifted by one-stage wired-OR logic circuit in order to assure the stable operation of the cascode type sense amplifier.