Abstract: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

Abstract: An electrophotographic photoreceptor comprises: an electroconductive support; and a photosensitive layer on the electroconductive support, wherein the photosensitive layer having a dynamic hardness of from 20×109 to 150×109 N/m2 and an elastic deformation ratio of from 15 to 80%.

Abstract: A stay ring of a hydraulic turbine has: a ring-shaped upper wall, a ring-shaped lower wall arranged below the upper wall forming a ring-shaped flow channel between the upper wall and the lower wall; and stay vanes arranged in array with spaces in a peripheral direction in the ring-shaped flow channel and rigidly secured to the upper and lower walls. The upper wall and the lower wall are inclined so as to reduce height of the ring-shaped flow channel toward outlet at least near inlet end thereof. The straightening bodies are arranged along inner surfaces of the upper wall and the lower wall at least near inlet end to reduce inclination of water flow in the stay ring.

Abstract: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

Abstract: A storage medium having stored thereon a game program executable by a computer 21 of a game apparatus 1 including touch coordinate pair input means for outputting coordinate information based on a predetermined coordinate system in accordance with a touch operation performed by a player. A first object P1 and a second object P2 are displayed on a display screen based on first object position data DC3 and second object position data DC5. While input coordinate pairs are being detected, the first object position data DC3 is updated based on the input coordinate pairs. The second object position data DC5 is updated based on the first object position data DC3.

Abstract: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

Abstract: The present invention is provided for considerably shortening the construction time of a building that is applied to nuclear power plants. When constructing the building, megablocks having a height that extends to a plurality of floors are produced, and together with combining those megablocks, concrete is poured inside them to form a wall member composed of a megawall structure of steel plate reinforced concrete construction. Alternatively, in addition to the wall megablocks, floor megablocks for forming the floor member of the building are used, and together with combining those megablocks, concrete is poured inside or above them to form a structural member (wall member and floor member) composed of a megawall structure of steel plate reinforced concrete construction.

Abstract: In a plasma facing member exposed to a plasma beam of nuclear fusion reactors or the like, such as an electron beam, a tungsten layer is formed by the use of a CVD method and has a thickness of 500 micron meters or more. The tungsten layer may be overlaid on a substrate of molybdenum or tungsten and comprises included gases reduced to 2 ppm or less and impurities reduced to 2 ppm or less. The tungsten layer is specified by either a fine equi-axed grain structure or a columnar grain structure. Alternatively, the material of the substrate may be, for example, Cu alloy, stainless steel, Nb alloy, or V alloy.

Abstract: A helical gear tooth broach having an elongate body having a series of axially aligned and spaced teeth disposed thereon. The direction of tooth spaces or traces of the teeth in a longitudinally extending helical alignment and the direction of the gullets of the teeth in a side by side circumferentially extending helical arrangement are both oriented at a right-upward or a left-upward helix angle in common with each other.

Abstract: The present invention is provided for considerably shortening the construction time of a building that is applied to nuclear power plants. When constructing the building, megablocks having a height that extends to a plurality of floors are produced, and together with combining those megablocks, concrete is poured inside them to form a wall member composed of a megawall structure of steel plate reinforced concrete construction. Alternatively, in addition to the wall megablocks, floor megablocks for forming the floor member of the building are used, and together with combining those megablocks, concrete is poured inside or above them to form a structural member (wall member and floor member) composed of a megawall structure of steel plate reinforced concrete construction.

Abstract: There is provided a reactor building of steel concrete construction, which comprises a steel concrete containment vessel constructed on the center of a footing slab and also composed of a pair of relatively confronting steel plates and concrete placed in a space between the steel plates. The reactor building is constructed on the outer circumference of the same footing slab and is also composed of a pair of relatively confronting steel plates and concrete placed in a space between the steel plates. The containment vessel is separated from partial slabs among a plurality of slabs of the reactor building placed around the containment vessel or all the slabs of the reactor building.

Abstract: There is provided a delay time calculation method, which simplifies a delay time calculation of an interconnection wiring which includes inductance, within a semiconductor integrated circuit, so that the calculation can be executed by use of the delay time calculating CAD tool used in the prior art.

Abstract: A phase-difference detector which uses a clock signal whose frequency is half the data rate, receives data at both rise timing and decay timing of the clock signal, and outputs phase-difference information between the data input signal and the clock signal.

Abstract: An electronic component composed of alternating internal electrodes in a ceramic material, the internal electrodes being electrically connected to an external electrode on each end of the ceramic material. The ceramic surface is porous and the surface between the external electrodes is impregnated with an insulating layer that also covers the surface of the body and the edges of the external electrodes to prevent water from finding its way through the edge of the external electrode.

Abstract: The present invention aims to present an electronic component which is free from the fear of sneaking-in of water etc. from the edge of electrode, by covering the electrode edge with resin. For the purpose, external electrodes (3) are formed at both ends of varistor (1) comprised of ceramic sheet (1a) and internal electrode (2) laminated alternately, and then, a within-the-surface insulation layer (30) is formed by covering the porous surface inside the varistor (1), or filling the porosity, with silicone resin, and an outside-the-surface insulation layer (31) is formed covering the surface of varistor (1) and the edge of external electrode (3).

Abstract: A duty ratio correction circuit includes a pair of circuit blocks each having an input stage inverter for receiving one of complementary clock signals, a first waveform correction circuit for receiving an output from a corresponding one of the input stage inverter, and a second waveform correction circuit for receiving the other of the complementary signals. Each of the waveform correction circuits has a lower output impedance at an initial stage of signal transition of the input signal and a higher output impedance at a subsequent stage of the signal transition.

Abstract: In a plasma facing member exposed to a plasma beam of nuclear fusion reactors or the like, such as an electron beam, a tungsten layer is formed by the use of a CVD method and has a thickness of 500 micron meters or more. The tungsten layer may be overlaid on a substrate of molybdenum or tungsten and comprises included gases reduced to 2 ppm or less and impurities reduced to 2 ppm or less. The tungsten layer is specified by either a fine equi-axed grain structure or a columnar grain structure. Alternatively, the material of the substrate may be, for example, Cu alloy, stainless steel, Nb alloy, or V alloy.

Abstract: A helical gear tooth broach is provided which does not require to clamp strongly the work to be broached by a special clamping device, and which does not perform an intermittent cutting action against the work. A gear tooth broach is provided having an elongate body having a series of axially aligned and spaced teeth disposed thereon. The direction of tooth spaces or traces of the teeth in a longitudinally extending helical alignment and the direction of the gullets of the teeth in a general side by side circumferentially extending helical arrangement are both oriented to the same hand of helix angle.

Abstract: In a plasma facing member exposed to a plasma beam of nuclear fusion reactors or the like, such as an electron beam, a tungsten layer is formed by the use of a CVD method and has a thickness of 500 micron meters or more. The tungsten layer may be overlaid on a substrate of molybdenum or tungsten and comprises included gases reduced to 2 ppm or less and impurities reduced to 2 ppm or less. The tungsten layer is specified by either a fine equi-axed grain structure or a columnar grain structure. Alternatively, the material of the substrate may be, for example, Cu alloy, stainless steel, Nb alloy, or V alloy.

Abstract: In a parallel-to parallel converter for converting an “m”-bit parallel signal into an “n”-bit parallel signal, a common multiple register has a bit width which is a common multiple of “m” and “n”. An input selector is connected to an input of the common multiple register, and writes the “m”-bit parallel signal into the common multiple register at a predetermined frequency. An output selector is connected to an output o f the common multiple register, and reads the “n”-bit parallel signal from the common multiple register at a frequency equal to m/n times the predetermined frequency.