Abstract: A fuel cell separator includes an electrically-conductive base substrate and a carbon film formed on the base substrate. The carbon film includes a first layer formed closest to the base substrate, and a second layer formed farthest from the base substrate. A diameter of carbon particles included in the first layer is 19 nm or less, and is smaller than a diameter of carbon particles included in a layer of the carbon film other than the first layer, and a diameter of the carbon particles included in the second layer is 40 nm or less.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: The present disclosure provides a layout of a semiconductor integrated circuit device that can assure a lot of substrate contact regions, and can surely suppress latch-up without increasing an area of a whole semiconductor integrated circuit and without significantly decreasing a decoupling capacitance element. In a margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on a P-type well. In the margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on an N-type well.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: The oriented amorphous carbon film contains C as a main component, 3 to 20 at. % of N, and more than 0 at. % and not more than 20 at. % of H, and when the total amount of the C is taken as 100 at. %, the amount of C having an sp2 hybrid orbital (Csp2) being not less than 70 at. % and less than 100 at. %, and (002) planes of graphite being oriented along a thickness direction. This film has a novel structure and exhibits a high electric conductivity. This film can be formed by DC plasma CVD method in which an electric discharge is generated by applying a voltage of not less than 1500 V to reaction gas including at least one kind of compound gas selected from gas of a carbocyclic compound containing Csp2 and gas of an N-containing heterocyclic compound containing Csp2, and nitrogen and/or silicon, and nitrogen gas.

Abstract: A bipolar plate for a fuel cell comprises a substrate formed of stainless steel; an oriented amorphous carbon film formed at least on a surface of the substrate facing an electrode, and containing C as a main component, 3 to 20 at. % of N, and more than 0 at. % and not more than 20 at. % of H, and when the total amount of the C is taken as 100 at. %, the amount of C having an sp2 hybrid orbital (Csp2) being not less than 70 at. % and less than 100 at. %, and (002) planes of graphite being oriented along a thickness direction; a mixed layer generated in an interface between the substrate and the oriented amorphous carbon film and containing at least one kind of constituent atoms of each of the substrate and the oriented amorphous carbon film; and a plurality of projections protruding from the mixed layer into the oriented amorphous carbon film and having a mean length of 10 to 150 nm.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: Power supply plugs, which couple a power supply active region to a power supply metal interconnect, include a plurality of first plugs, which are arranged at first pitches of a predetermined length, and a second plug, which is spaced apart from the closest one of the first plugs by a center-to-center distance different from an integral multiple of the predetermined length. Among the power supply plugs, the second plug is closest to a third plug, which is an interconnect plug closest to the power supply active region and the power supply metal interconnect.

Abstract: An amorphous carbon film contains carbon as a main component, not more than 30 at. % of hydrogen, not more than 20 at. % of nitrogen and not more than 3 at. % of oxygen (all excluding 0 at. %), and when the total amount of the carbon is taken as 100 at. %, the amount of carbon having an sp2 hybrid orbital is not less than 70 at. % and less than 100 at. %. Nitrogen and oxygen are concentrated on a surface side of the film and when detected from a surface layer by X-ray photoelectron spectroscopy, oxygen content ratio is not less than 4 at. % and not more than 15 at. % and nitrogen content ratio is not less than 10 at. % and not more than 30 at. %. The amorphous carbon film attains both electric conductivity and hydrophilicity and exhibits suitable surface characteristics to a fuel cell bipolar plate, etc.

Abstract: The present disclosure provides a layout of a semiconductor integrated circuit device that can assure a lot of substrate contact regions, and can surely suppress latch-up without increasing an area of a whole semiconductor integrated circuit and without significantly decreasing a decoupling capacitance element. In a margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on a P-type well. In the margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on an N-type well.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.