Patents by Inventor Kazuyuki Nakanishi

Kazuyuki Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110169099
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuyuki NAKANISHI
  • Publication number: 20110133253
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Application
    Filed: February 3, 2011
    Publication date: June 9, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuyuki NAKANISHI, Masaki Tamaru
  • Patent number: 7939858
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Patent number: 7850795
    Abstract: While securing the building-up ability and crack resistance, to provide a build-up wear-resistant copper alloy and valve seat. The build-up wear-resistant copper alloy and valve seat are characterized by having a composition of nickel: 5.0-24.5%, iron: 3.0-20.0%, silicon: 0.5-5.0%, boron: 0.05-0.5%, chromium: 0.3-5.0%, one member or two members or more selected from the group consisting of molybdenum, tungsten and vanadium: 3.0-20.0%, by weight %, and the balance being copper and inevitable impurities.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: December 14, 2010
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Minoru Kawasaki, Takao Kobayashi, Tadashi Oshima, Kazuyuki Nakanishi
  • Publication number: 20100308377
    Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
    Type: Application
    Filed: August 17, 2010
    Publication date: December 9, 2010
    Inventors: Kazuyuki NAKANISHI, Hidetoshi Nishimura, Tomoaki Ikegami
  • Patent number: 7833626
    Abstract: An amorphous carbon film includes carbon as a major component, and silicon in an amount of from 0.1 atomic % or more to 10 atomic % or less when the entire amorphous carbon film is taken as 100 atomic %. The carbon is composed of carbon having an sp2 hybrid orbital in an amount of from 60 atomic % or more to 90 atomic % or less when the entire carbon amount is taken as 100 atomic %. Also disclosed is a process for producing the amorphous carbon film.
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Takashi Iseki, Hideo Tachikawa, Hiroyuki Mori, Kazuyuki Nakanishi, Munehisa Matsui, Shintaro Igarashi, Fumio Shimizu, Yoshinari Tsuchiya, Tadashi Oshima
  • Patent number: 7815756
    Abstract: This is to provide a build-up wear-resistant copper-based alloy, which is advantageous for enhancing the cracking resistance and machinability, which is appropriate for cases of building up to form built-up layers especially, and which is equipped with the wear resistance, cracking resistance and machinability combinedly in a well balanced manner. A build-up wear-resistant copper-based alloy is characterized in that it has a composition, which includes nickel: 5.0-20.0%; silicon: 0.5-5.0%; manganese: 3.0-30.0%; and an element, which combines with manganese to form a Laves phase and additionally to form silicide: 3.0-30.0%; by weight %, and inevitable impurities; and additionally the balance being copper. The element can be one member or two or more members of titanium, hafnium, zirconium, vanadium, niobium and tantalum.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: October 19, 2010
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Minoru Kawasaki, Tadashi Oshima, Takao Kobayashi, Kazuyuki Nakanishi
  • Patent number: 7815028
    Abstract: A friction clutch includes an iron inner clutch plate and two iron outer clutch plates. Each clutch plate has a sliding surface that friction-engages with the other clutch plates. A diamond-like carbon film containing silicon, which functions as a solid lubricant, is formed on the sliding surface of each outer clutch plate through a conventional method such as plasma chemical vapor deposition. The diamond-like carbon film contains 1 wt % to 80 wt % of silicon. A coupling device includes a pilot clutch mechanism that has the friction clutch and an electromagnetic actuator. As a result, the friction clutch has an improved resistance to wear, and the coupling device is durable.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: October 19, 2010
    Assignee: JTEKT Corporation
    Inventors: Junji Ando, Naoyuki Sakai, Toshifumi Sakai, Hajime Fukami, Toshiyuki Saito, Koji Nishi, Kazuyuki Nakanishi, Hiroyuki Mori, Hideo Tachikawa
  • Patent number: 7803433
    Abstract: An amorphous carbon film forming apparatus according to the present invention is characterized by being provided with a film forming furnace 11; plural workpiece fixtures 23 for supporting plural plate-like workpieces 22 in a state that the same are piled up vertically in parallel with the interval between facing surfaces of two vertically adjoining of the plate-like workpieces 22 being in a range of 2 to 30 millimeters, the plural workpiece fixtures 23 being arranged within the film forming furnace 11 at a regular angular interval on a circle and being connected to a negative electrode; nozzles 31, 32 provided for supplying a processing gas and including at least one nozzle arranged at a center of the circle on which the plural workpiece fixtures 23 are arranged and plural nozzles arranged at a regular angular interval on another circle which surrounds the workpieces fixtures 23 radially outside thereof; and a plasma power supply connected to at least the workpiece fixtures 23.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: September 28, 2010
    Assignee: JTEKT Corporation
    Inventors: Junji Ando, Naoyuki Sakai, Toshiyuki Saito, Kazuyuki Nakanishi, Hiroyuki Mori, Hideo Tachikawa, Kyouji Itou, Mikio Fujioka, Yoshiyuki Funaki
  • Patent number: 7800140
    Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Hidetoshi Nishimura, Tomoaki Ikegami
  • Patent number: 7721642
    Abstract: To provide a sliding member that exhibits excellent durability and is free of lead. A swash plate for a compressor as the sliding member of the invention contains a base material having on the surface thereof a sliding layer constituting at least a sliding surface, on which shoes slide. The sliding layer contains a first layer that contains an amorphous hard carbon (diamond-like carbon) film containing Si (DLC-Si film) and is formed on the base material, and a second layer that is formed on the first layer and contains polyamideimide (PAI) containing a solid lubricant such as MoS2.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: May 25, 2010
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Takahiro Sugioka, Takayuki Kato, Shuichi Yasuda, Atsushi Saito, Masahiro Suzuki, Hitotoshi Murase, Takashi Iseki, Hideo Tachikawa, Kazuyuki Nakanishi, Takao Kobayashi, Ken-ichi Suzuki
  • Patent number: 7677375
    Abstract: A drive force transmission device has an outer clutch plate and an inner clutch plate, which are rotatable relative to each other about a common rotational axis. The inner and outer clutch plates become frictionally engaged with each other with lubricant oil provided in between. The outer and inner clutch plates each have a sliding surface. The sliding surfaces face each other. A diamond-like carbon film is formed on the sliding surface of the outer clutch plate. Fine grooves are formed in the sliding surface of the inner clutch plate. The proportion of the sliding area to the sliding surface of the inner clutch plate at the initial stage of use is 55 to 90%.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 16, 2010
    Assignee: JTEKT Corporation
    Inventors: Junji Ando, Naoyuki Sakai, Toshifumi Sakai, Toshiyuki Saito, Hajime Fukami, Kazuyuki Nakanishi, Hiroyuki Mori, Hideo Tachikawa
  • Publication number: 20100001404
    Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
    Type: Application
    Filed: August 17, 2009
    Publication date: January 7, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
  • Publication number: 20090289308
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Application
    Filed: August 5, 2009
    Publication date: November 26, 2009
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuyuki NAKANISHI
  • Patent number: 7592676
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Publication number: 20090169968
    Abstract: The amorphous carbon film of the present invention is an amorphous carbon film comprising carbon and hydrogen, wherein the amorphous carbon film contains not more than 30 atomic % (excluding 0%) of hydrogen and, when the entire amount of the carbon is taken as 100 atomic %, carbon having an sp2 hybrid orbital is present in an amount of not less than 70 atomic % and less than 100 atomic %. Conductivity is imparted to an amorphous carbon film by controlling the contents of hydrogen, Csp3 and the like to increase a structure comprising Csp2. This amorphous carbon film can be formed by plasma CVD using a reaction gas containing one or more gases selected from a carbocyclic compound gas containing carbon having an sp2 hybrid orbital, and a heterocyclic compound gas containing carbon having an sp2 hybrid orbital and silicon and/or nitrogen. By forming the amorphous carbon film on a surface of a substrate, a conductive member can be obtained.
    Type: Application
    Filed: May 22, 2007
    Publication date: July 2, 2009
    Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Takashi Iseki, Yuka Yamada, Kazuyuki Nakanishi, Tadashi Oshima, Hiroyuki Mori, Toshio Horie, Ken-ichi Suzuki, Gaku Kitahara
  • Patent number: 7537835
    Abstract: Under wet sliding conditions using drivetrain system lubricating oils, a high frictional sliding member exhibiting a high friction coefficient, a favorable ??v characteristic stably, excellent wear resistance, and low mating-member aggressiveness is provided. The present invention is a wet sliding member comprising: a substrate composed of metal, ceramics, or resin; and an amorphous hard carbon film formed integrally on a surface of the substrate, having a surface, at least a part of which is turned into a sliding surface for sliding under wet conditions, and containing at least either one of Si and N in an amount of from 1 to 50 atomic %.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 26, 2009
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Hiroyuki Mori, Hideo Tachikawa, Masaru Okuyama, Mamoru Tohyama, Toshihide Ohmori, Kazuyuki Nakanishi
  • Patent number: 7507305
    Abstract: This aims to provide a wear-resistant copper-based alloy, which is advantages in not only enhancing wear resistance in a high temperature range but also enhancing crack resistance and machinability and which is especially suitable for forming a cladding layer. The wear-resistant copper-based alloy comprises, by weight, 4.7 to 22.0% nickel, 0.5 to 5.0% silicon, 2.7 to 22.0% iron, 1.0 to 15.0% chromium, 0.01 to 2.00% cobalt, 2.7 to 22.0% one or more of tantalum, titanium, zirconium and hafnium, and the balance of copper with inevitable impurities.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 24, 2009
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Minoru Kawasaki, Tadashi Oshima, Takao Kobayashi, Kazuyuki Nakanishi, Hideo Tachikawa
  • Patent number: 7475375
    Abstract: A rectangular opening is formed in a power supply line which is shared between cell rows. A connection to a substrate potential supply line is ensured in the rectangular opening. Specifically, a semiconductor device includes a plurality of cell rows each including a plurality of standard cells arranged therein, a first power supply line for supplying a first potential to each of the standard cells, and a second power supply line for supplying a second potential to each of the standard cells, the second power supply line being electrically separated from the first power supply line. At least two standard cells share the first power supply line through a first interconnect provided in an interconnect layer and share the second power supply line through a second interconnect provided in the interconnect layer.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Publication number: 20080317976
    Abstract: An amorphous carbon film forming apparatus according to the present invention is characterized by being provided with a film forming furnace 11; plural workpiece fixtures 23 for supporting plural plate-like workpieces 22 in a state that the same are piled up vertically in parallel with the interval between facing surfaces of two vertically adjoining of the plate-like workpieces 22 being in a range of 2 to 30 millimeters, the plural workpiece fixtures 23 being arranged within the film forming furnace 11 at a regular angular interval on a circle and being connected to a negative electrode; nozzles 31, 32 provided for supplying a processing gas and including at least one nozzle arranged at a center of the circle on which the plural workpiece fixtures 23 are arranged and plural nozzles arranged at a regular angular interval on another circle which surrounds the workpieces fixtures 23 radially outside thereof; and a plasma power supply connected to at least the workpiece fixtures 23.
    Type: Application
    Filed: February 12, 2004
    Publication date: December 25, 2008
    Applicant: TOYODA KOKI KABUSHIKI KAISHA
    Inventors: Junji Ando, Naoyuki Sakai, Toshiyuki Saito, Kazuyuki Nakanishi, Hiroyuki Mori, Hideo Tachikawa, Kyouji Itou, Mikio Fujioka, Yoshiyuki Funaki