Abstract: The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Abstract: A power supply apparatus 200 comprises an energy supplying circuit 210 for supplying energy at a predetermined timing, and an energy preserving circuit 220 for receiving the energy supplied from the energy supplying circuit 210 and preserving the energy. The energy preserving circuit 220 includes an inductor 221, a capacitance 223 connected to one end of the inductor 221 at a node 222, and a capacitance 225 connected to the other end of the inductor 221 at a node 224. Energy is supplied to a load via at least one of the node 222 and the node 224.

Abstract: Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.

Abstract: A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed.

Abstract: According to the present invention, a signal transmission circuit for receiving an input signal and outputting an output signal corresponding to the input signal is provided. The signal transmission circuit includes: a first capacitance; an electric charge supply section for supplying electric charge corresponding to the input signal to the first capacitance; a second capacitance; and a transfer section for transferring the electric charge from the first capacitance to the second capacitance. In the signal transmission circuit, the second capacitance is larger than the first capacitance.

Abstract: A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

Abstract: There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals.

Abstract: Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: The A/D converter realizes a high-rate and high-precision A/D conversion using amplifier circuits. Each amplifier circuit amplifies a difference between the voltage of an analog signal to be converted and a predetermined reference voltage. Each bank of holding circuits holds the output signals of an oscillator circuit, the levels of which signals are variable with the passage of time, when the output voltage of the associated amplifier circuit exceeds a predetermined value. The signals held in each said bank of holding circuits are output as a value representing the amplification time of the associated amplifier circuit.

Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption.An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.

Abstract: An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined

Abstract: A low-cost permanent magnet dynamo-electric machine which can prevent an occurrence of a chip in a permanent magnet and is superior in the ease of fabricating the machine. This machine has an elastic catching member consisting of a ring-like portion and a plurality of protruding pieces axially projected from this ring-like portion. This machine further has a yoke, onto the inner circumferential surface of which a plurality of auxiliary poles are welded at an isotropic angular pitch. Further, in this machine, each of permanent magnets has a side surface brought into abutting engagement with the corresponding auxiliary pole. Moreover, the protruding pieces of the elastic catching member are forced into a space between the other side surface of each of the permanent magnets and the adjoining auxiliary pole, so that the plurality of the permanent magnets surround an armature.

Abstract: A planetary gear reduction mechanism permitting easy mounting of a plate that separates a gear reduction section from a motor section. A flange portion 20 that is integrally formed with an output shaft rotation axis 11 is provided on its rear side a ring of support pins 21 having an open-ended cylinder shape and circumferentially equally spaced in a circle. A plate 22 has on its front side of the flange portion 22a a ring of projections 22b circumferentially equally spaced, and the projections 22b are engaged with the support pins 21. With planetary gears 7 attached onto the support pins 21, the plate 22 is mounted by press-fit inserting the projections 22b into the openings of the support pins 21.

Abstract: A planetary gear speed reducer and a machining method for a planetary gear supporting pin which enable the supporting pin to be formed as an integral part of a flange section by forging so as to reduce the number of parts, permit greater ease of assembly, and achieve lower cost and also to make it easier to obtain perpendicularity of the supporting pin with respect to the flange section. A plurality of supporting pins which are formed in hollow cylindrical shapes are pressed out at equal angle pitches on the same circumference on the rear end surface of a flange section which is made integral with an output rotary shaft. The front end surface of the flange section has recessed sections which are formed coaxially with the supporting pins. The outside diameters of the supporting pins are made smaller than the inside diameters of the recessed sections. The distal ends of the supporting pins are open and the hollow sections of the supporting pins are communicated with the recessed sections.