Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

Abstract: An image forming apparatus includes an image bearing member configured to bear a toner image on a surface thereof. A charging mechanism is configured to uniformly charge the surface of the image bearing member. An intermediate transfer mechanism is configured to transfer the toner image from the image bearing member onto an image receiver. A cleaning mechanism is configured to clean the surface of the image bearing member after the toner image is transferred onto the image receiver. A lubricant supplying mechanism is configured to supply a lubricant contained therein onto the surface of the image bearing member and form a thin layer using a lubricating blade. The lubricant supplying mechanism is disposed between the cleaning mechanism and the charging mechanism.

Abstract: A first display displays a predetermined number of symbols among a plurality of symbols including at least one special symbol. A storage stores a first number of times that a special symbol combination is appeared on the first display, the special symbol combination includes a first symbol combination in which at least one special symbol is included and a second symbol combination which is a predetermined combination of the symbols. A determinant determines whether the first number of times stored in the storage is not less than a second, predetermined number. A signal generator generates an award signal for causing the gaming machine to provide an award to a player in accordance with the special symbol combination displayed on the first display, when the determinant determines the first number of times is not less than the second number of times.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.

Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: A method of increasing proliferation of cells which comprises adding to cells a cellular proliferating amount of a primary hydroxyl group of N-acetylglucosamine selectively desulfated heparin having the following characteristics for an enzyme digestion product of the heparin: (1) contents of unsaturated disaccharides of the following formulae (a) and (b): measured by high performance liquid chromatography in the enzyme digestion product of the selectively desulfated heparin are less than 40% and 30 to 67%, respectively, (2) a content of disaccharides containing an N-substituted sulfate group is 75 to 95%, and (3) the weight average molecular weight Mw is 4,000 to 30,000 dalton.

Abstract: A nonvolatile memory, provided with nonvolatile memory cells, has a plurality of memory banks each of which can perform memory operations independently of others, and a control unit for controlling the memory operations of the memory banks. The control unit is capable of controlling an interleave operation by which, even during a memory operation in response to an operational instruction designating one of the memory banks, a memory operation in response to another operational instruction designating another memory bank can be started, and a parallel operation by which both memory banks are caused to perform memory operations in parallel when, before a memory operation in response to an operational instruction designating one of the memory banks is started, another memory operation designating another memory bank is instructed. Each memory bank is provided with a status register, and the status of memory operation in each memory bank is reflected in the corresponding status register.

Abstract: A memory bank comprises nonvolatile memory sections and two buffer sections to respectively store information of access unit of the nonvolatile memory sections. In response to the instruction of access operation, the memory bank performs data transfer between one buffer section of the memory bank and the nonvolatile memory section. In parallel to this data transfer, the memory bank also enables control of interleave operation to perform data transfer between the other buffer section of the relevant memory bank and the external side. Accordingly, high speed access can be realized by conducting in parallel the data transfer between the nonvolatile memory section and the buffer section and data transfer between the buffer section and the external side in the interleave operation. Moreover, high speed write and read access to the nonvolatile memory section can also be realized.

Abstract: Touch-responsive data transmission system for elongating transceiver battery life and assuring one-touch data transmission includes a first transceiver worn on user and a second transceiver connected to equipment utilizing first transceiver data. User contacts first transceiver signal and ground electrodes and touches a second transceiver touch electrode to establish a signal path through user. First transceiver includes a detector for detecting a start signal from the second transceiver signal electrode. Second transceiver includes a generator for generating the start signal upon touching the touch electrode. Receiving the start signal, circuit elements responsible for data transmission are battery-energized to start data transmission from first to second transceivers. Circuit elements responsible for transmitting data remain deenergized until user touches the second transceiver touch electrode to save energy during non-operation and prolong first transceiver battery life.

Abstract: A status register within a non-volatile semiconductor memory device chip is provided with a bit indicating whether an access is possible from the external side of the chip or not and a controller for instructing the write process to the non-volatile semiconductor device issues again a write process instruction to the same area depending on the condition of the bit of the status register. Thereby, reduction of effective memory area due to an accidental write error generated can be prevented in the system utilizing an electrically erasable and programmable non-volatile semiconductor memory device such as a flash memory.

Abstract: The bit (B6) indicating whether there is the possibility or not to normally complete the write operation by executing again the write operation is provided, together with the bit (B7) indicating whether the access is possible or not from the external side of the chip and the bit (B4) indicating whether the write operation is normally completed or not, to the status register within a non-volatile semiconductor memory device. Accordingly, it can be prevented that the effective memory capacity is reduced with an accidental write error in the electrically programmable and erasable non-volatile semiconductor memory device such as a flash memory.

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A memory bank comprises nonvolatile memory sections and two buffer sections to respectively store information of access unit of the nonvolatile memory sections. In response to the instruction of access operation, the memory bank performs data transfer between one buffer section of the memory bank and the nonvolatile memory section. In parallel to this data transfer, the memory bank also enables control of interleave operation to perform data transfer between the other buffer section of the relevant memory bank and the external side. Accordingly, high speed access can be realized by conducting in parallel the data transfer between the nonvolatile memory section and the buffer section and data transfer between the buffer section and the external side in the interleave operation. Moreover, high speed write and read access to the nonvolatile memory section can also be realized.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: This invention relates to a process for producing a desulfated polysaccharide, which comprises reacting a sulfated polysaccharide having a saccharide in which a primary hydroxyl group is sulfated, as a constituent sugar, with a silylating agent represented by the following formula (I) 1