Abstract: The bit (B6) indicating whether there is the possibility or not to normally complete the write operation by executing again the write operation is provided, together with the bit (B7) indicating whether the access is possible or not from the external side of the chip and the bit (B4) indicating whether the write operation is normally completed or not, to the status register within a non-volatile semiconductor memory device. Accordingly, it can be prevented that the effective memory capacity is reduced with an accidental write error in the electrically programmable and erasable non-volatile semiconductor memory device such as a flash memory.

Abstract: This invention relates to a process for producing a desulfated polysaccharide, which comprises reacting a sulfated polysaccharide having a saccharide in which a primary hydroxyl group is sulfated, as a constituent sugar, with a silylating agent represented by the following formula (I) wherein R1s are the same or different and each represent a hydrogen atom or a halogen atom, R2 represents a lower alkyl group, and R3s are the same or different and each represent a lower alkyl group, an aryl group or a halogen atom, and a desulfated heparin obtained by this production process.

Abstract: The meal advice system of the present invention provides appropriate next meals in consideration of the previous meal taken by a dieter. The previous meals are transmitted as an image data from a dieter terminal to a server which responds to relay the image data to an analyst terminal for requesting the analysis of foods contained in the meal. The analysis result is transmitted back to the server where nutrient constituents of the analysis result are compared with prescribed nutrient amounts needed for the dieter to select a collection of the next meals containing foods compensating the deficient nutrient amounts. Then, a proposed menu containing the collection of the meals is transmitted to the dieter and/or a meal assistant who serves the meal to the dieter.

Abstract: A communication system includes a transmitting device, a receiving device having receiving device for receiving data transmitted by said transmitting device and managing device for managing received data, detecting device for detecting whether or not communication of data between said transmitting device and said receiving device is permitted, said detecting device being provided with at least one of said transmitting device and said receiving device, wherein when said detecting device detects a fact that communication of data is permitted, said transmitting device starts transmitting data to said receiving device.

Abstract: In the nonvolatile semiconductor memory device, a plurality of threshold voltages are associated with the programming of multi-valued information in one memory cell, data is first written into a memory cell having a threshold voltage which is the lowest or furthest away from the threshold voltage corresponding to the erase level, and data is successively written into memory cells having higher threshold voltages, namely, threshold voltages that are successively closer to the erase level, thereby overcoming threshold voltage fluctuations attributed to word line disturbance.

Abstract: The bit (B6) indicating whether there is the possibility or not to normally complete the write operation by executing again the write operation is provided, together with the bit (B7) indicating whether the access is possible or not from the external side of the chip and the bit (B4) indicating whether the write operation is normally completed or not, to the status register within a non-volatile semiconductor memory device. Accordingly, it can be prevented that the effective memory capacity is reduced with an accidental write error in the electrically programmable and erasable non-volatile semiconductor memory device such as a flash memory.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store, multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: A first display displays a predetermined number of symbols among a plurality of symbols including at least one special symbol. A storage stores a first number of times that a special symbol combination is appeared on the first display, the special symbol combination includes a first symbol combination in which at least one special symbol is included and a second symbol combination which is a predetermined combination of the symbols. A determinant determines whether the first number of times stored in the storage is not less than a second, predetermined number. A signal generator generates an award signal for causing the gaming machine to provide an award to a player in accordance with the special symbol combination displayed on the first display, when the determinant determines the first number of times is not less than the second number of times.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A status register within a non-volatile semiconductor memory device chip is provided with a bit indicating whether an access is possible from the external side of the chip or not and a controller for instructing the write process to the non-volatile semiconductor device issues again a write process instruction to the same area depending on the condition of the bit of the status register. Thereby, reduction of effective memory area due to an accidental write error generated can be prevented in the system utilizing an electrically erasable and programmable non-volatile semiconductor memory device such as a flash memory.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: A method for producing an N-acetyllactosamine oligosaccharide, comprising the steps of: adjusting a sulfate group content of keratan sulfate; allowing an enzyme having an ability to cleave a glycosidic linkage of keratan sulfate to act on the keratan sulfate with the adjusted sulfate group content to obtain a sulfated N-acetyllactosamine oligosaccharide; and completely desulfating said sulfated N-acetyllactosamine oligosaccharide.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: The bit (B6) indicating whether there is the possibility or not to normally complete the write operation by executing again the write operation is provided, together with the bit (B7) indicating whether the access is possible or not from the external side of the chip and the bit (B4) indicating whether the write operation is normally completed or not, to the status register within a non-volatile semiconductor memory device. Accordingly, it can be prevented that the effective memory capacity is reduced with an accidental write error in the electrically programmable and erasable non-volatile semiconductor memory device such as a flash memory.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: A progressive gaming system comprises a plurality of gaming machines, each of which is constructed to perform a predetermined main game in response to an operation of a player and gives a prize to the player when a winning combination is formed in the main game; and a progressive unit for counting an amount of a progressive bonus based on an amount of a bet in the main game played in each of the gaming machines and controlling a payment of the progressive bonus in association with a result of the main game. Each of the gaming machines or the progressive unit is provided with a judging device for judging whether or not the result of the main game played in each of the gaming machines meets a predetermined bonus chance condition for proceeding to a lottery game.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.