Patents by Inventor Ken-Hsien Hsieh

Ken-Hsien Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200013630
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Publication number: 20200006078
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Application
    Filed: January 4, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
  • Publication number: 20200004137
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
  • Publication number: 20190378712
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 12, 2019
    Inventors: Yung-Sung YEN, Chun-Kuang CHEN, Ko-Bin KAO, Ken-Hsien HSIEH, Ru-Gun LIU
  • Publication number: 20190371606
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10483120
    Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
  • Publication number: 20190290246
    Abstract: An assisted detection system of breast tumor includes an image capturing unit and a non-transitory machine readable medium. The non-transitory machine readable medium storing a program which, when executed by at least one processing unit, determines a breast tumor type of the subject and predicts a probability of a tumor location of the subject. The program includes a reference database obtaining module, a first image preprocessing module, an autoencoder module, a classifying module, a second image preprocessing module and a comparing module.
    Type: Application
    Filed: December 12, 2018
    Publication date: September 26, 2019
    Inventors: Tzung-Chi Huang, Ken Ying-Kai Liao, Jiaxin Yu, Yang Hsien Lin, Po-Hsin Hsieh
  • Patent number: 10420535
    Abstract: An assisted detection system of breast tumor includes an image capturing unit and a non-transitory machine readable medium. The non-transitory machine readable medium storing a program which, when executed by at least one processing unit, determines a breast tumor type of the subject and predicts a probability of a tumor location of the subject. The program includes a reference database obtaining module, a first image preprocessing module, an autoencoder module, a classifying module, a second image preprocessing module and a comparing module.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 24, 2019
    Assignee: CHINA MEDICAL UNIVERSITY HOSPITAL
    Inventors: Tzung-Chi Huang, Ken Ying-Kai Liao, Jiaxin Yu, Yang Hsien Lin, Po-Hsin Hsieh
  • Patent number: 10418252
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10410913
    Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Chih-Ming Lai, Ken-Hsien Hsieh, Tsai-Sheng Gau, Ru-Gun Liu
  • Patent number: 10410863
    Abstract: The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10388523
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
  • Publication number: 20190252200
    Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
  • Publication number: 20190146333
    Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 16, 2019
    Inventors: Ken-Hsien HSIEH, Ru-Gun LIU, Wei-Shuo SU
  • Publication number: 20190146355
    Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.
    Type: Application
    Filed: August 7, 2018
    Publication date: May 16, 2019
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 10276377
    Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Sung Yen, Yu-Hsun Chen, Chen-Hau Wu, Chun-Kuang Chen, Ta-Ching Yu, Ken-Hsien Hsieh, Ming-Jhih Kuo, Ru-Gun Liu
  • Patent number: 10276394
    Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
  • Patent number: 10274829
    Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu, Chih-Ming Lai
  • Publication number: 20190122887
    Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
  • Publication number: 20190080921
    Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu