Patents by Inventor Ken-Hsien Hsieh
Ken-Hsien Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11467509Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.Type: GrantFiled: March 29, 2021Date of Patent: October 11, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
-
Publication number: 20220285168Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
-
Publication number: 20220283494Abstract: A method comprises generating an original layout having main pattern sets; simulating a first energy distribution of the original layout on a pupil plane of a lithography system, wherein the first energy distribution has a first wavefront; generating a first modified layout by inserting dummy pattern sets in regions of the original layout that are not occupied by the main pattern sets; simulating a second energy distribution of the first modified layout on a pupil plane of a lithography system; determining whether a second wavefront of the simulated second energy distribution is more homogeneous than the first wavefront of the first energy distribution; and performing a first lithography process using a first photomask having the first modified layout in response to second wavefront of the simulated second energy distribution being determined as more homogeneous than the first wavefront of the first energy distribution.Type: ApplicationFiled: July 9, 2021Publication date: September 8, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Min WANG, Ken-Hsien HSIEH
-
Patent number: 11342193Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.Type: GrantFiled: September 28, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin
-
Publication number: 20220155692Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
-
Patent number: 11294286Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.Type: GrantFiled: February 27, 2019Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai, Ken-Hsien Hsieh, Shih-Ming Chang, Yuan-Te Hou
-
Patent number: 11243472Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.Type: GrantFiled: June 8, 2020Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
-
Publication number: 20210356872Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Inventors: Ken-Hsien HSIEH, Ru-Gun LIU, Wei-Shuo SU
-
Publication number: 20210286274Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.Type: ApplicationFiled: March 29, 2021Publication date: September 16, 2021Inventors: Chih-Jie LEE, Shih-Chun HUANG, Shih-Ming CHANG, Ken-Hsien HSIEH, Yung-Sung YEN, Ru-Gun LIU
-
Patent number: 11079685Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.Type: GrantFiled: April 30, 2018Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien Hsieh, Ru-Gun Liu, Wei-Shuo Su
-
Publication number: 20210175081Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
-
Publication number: 20210132504Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.Type: ApplicationFiled: May 28, 2020Publication date: May 6, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien HSIEH, Shih-Ming CHANG, Wen LO, Wei-Shuo SU, Hua-Tai LIN
-
Patent number: 10962892Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.Type: GrantFiled: December 20, 2018Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
-
Patent number: 10957551Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).Type: GrantFiled: September 16, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
-
Patent number: 10930505Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.Type: GrantFiled: August 16, 2019Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
-
Publication number: 20210013048Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
-
Patent number: 10817635Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.Type: GrantFiled: September 17, 2018Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang
-
Patent number: 10790155Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.Type: GrantFiled: January 4, 2019Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin
-
Publication number: 20200301289Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
-
Publication number: 20200286738Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU