Patents by Inventor Ken-Hsien Hsieh
Ken-Hsien Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276394Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.Type: GrantFiled: September 14, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
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Patent number: 10274829Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.Type: GrantFiled: August 29, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu, Chih-Ming Lai
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Patent number: 10276377Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.Type: GrantFiled: May 11, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Sung Yen, Yu-Hsun Chen, Chen-Hau Wu, Chun-Kuang Chen, Ta-Ching Yu, Ken-Hsien Hsieh, Ming-Jhih Kuo, Ru-Gun Liu
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Publication number: 20190122887Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20190080921Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.Type: ApplicationFiled: September 14, 2017Publication date: March 14, 2019Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
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Publication number: 20190042685Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.Type: ApplicationFiled: September 17, 2018Publication date: February 7, 2019Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang
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Patent number: 10163634Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.Type: GrantFiled: May 11, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20180277358Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Inventors: Yung-Sung YEN, Chun-Kuang CHEN, Ko-Bin KAO, Ken-Hsien HSIEH, Ru-Gun LIU
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Patent number: 10083270Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.Type: GrantFiled: December 14, 2016Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Shuo-Yen Chou, Ru-Gun Liu
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Patent number: 10078718Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.Type: GrantFiled: June 10, 2016Date of Patent: September 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wan
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Patent number: 10032664Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.Type: GrantFiled: June 6, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20180174854Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Lin
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Publication number: 20180164695Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.Type: ApplicationFiled: August 29, 2017Publication date: June 14, 2018Inventors: Ken-Hsien HSIEH, Wen-Li CHENG, Pai-Wei WANG, Ru-Gun LIU, Chih-Ming LAI
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Publication number: 20180165397Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Shuo-Yen Chou, Ru-Gun Liu
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Patent number: 9984876Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.Type: GrantFiled: April 3, 2017Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20180138042Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.Type: ApplicationFiled: December 22, 2017Publication date: May 17, 2018Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 9852908Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.Type: GrantFiled: June 6, 2016Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20170338115Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.Type: ApplicationFiled: May 11, 2017Publication date: November 23, 2017Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20170338146Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.Type: ApplicationFiled: May 11, 2017Publication date: November 23, 2017Inventors: Yung-Sung Yen, Yu-Hsun Chen, Chen-Hau Wu, Chun-Kuang Chen, Ta-Ching Yu, Ken-Hsien Hsieh, Ming-Jhih Kuo, Ru-Gun Liu
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Patent number: 9773671Abstract: Provided is a material composition and method for inhibiting the printing of SRAFs onto a substrate including coating a substrate with a resist layer. After coating the substrate, the resist layer is patterned to form a main feature pattern and at least one sub-resolution assist feature (SRAF) pattern within the resist layer. The main feature pattern may include resist sidewalls and a portion of a layer underlying the patterned resist layer. In various examples, a material composition is deposited over the patterned resist layer and into each of the main feature pattern and the at least one SRAF pattern. Thereafter, a material composition development process is performed to dissolve a portion of the material composition within the main feature pattern and to expose the portion of the layer underlying the patterned resist layer.Type: GrantFiled: May 31, 2016Date of Patent: September 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Tze Chen, Chen-Hau Wu, Meng-Wei Chen, Kuei-Shun Chen, Yu-Chin Huang, Li-Hsiang Lai, Shih-Ming Chang, Ken-Hsien Hsieh