Abstract: A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacitor which is formed on a third interlayer insulation film covering the bit line; a capacitor contact which is formed through the third and second interlayer insulation film and makes a connection between the capacitor and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.

Abstract: The present invention pertains to a computing system having an input system with local storage interfaced with a computing device, wherein input information is transferred from the digitizer input system to the interfaced computing device based on an adaptive transfer policy that extends the battery life of the interfaced computing device. The interfaced computing device may be a PC. The digitizer input system can support automated, selective transfer policies based on the power management configuration of the PC interfaced with the digitizer input system and user-selected transfer policies.

Abstract: A powder for an underlayer of a coating-type magnetic recording medium comprises acicular iron oxide particles having an average major axis length in the range of 20-200 nm, has a specific surface area measured by the BET method of 30-100 m2/g and has a powder pH of not greater than 7. The underlayer powder preferably contains 0.1-5.0 wt % of P and optionally contains an amount of R (where R represents one or more rare earth elements, defined as including Y) such that R/Fe expressed in atomic percentage (at. %) is 0.1-10 at. %. The iron oxide powder enhances the properties required of a powder for forming the underlayer of a multi-layer structure coating-type magnetic recording tape, most notably the surface smoothness and strength of the tape.

Abstract: A powder for an underlayer of a coating-type magnetic recording medium, which powder comprises flat-acicular iron oxide particles having an average major axis length of 20-200 nm, a short axis cross-section taken perpendicularly to the long axis that has a long width and a short width, and a short axis cross-section ratio defined as the ratio of the long width to the short width that is greater than 1.3 and substantially uniform in the long axis direction, the powder having a specific surface area measured by the BET method of 30-100 m2/g. The underlayer powder preferably contains 0.1-5.0 wt % of P and, optionally, an amount of R(R representing one or more rare earth elements, defined as including Y) such that R/Fe expressed in atomic percentage (at. %) is 0.1-10 at. %.

Abstract: In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Abstract: The present invention pertains to an input system for inputting information from a user, the input device system including at least one sheet of a writing medium having a unique identifier located thereon, a stylus input device for writing on the writing medium and emitting one or more signals, a detector for detecting said unique page identifier and stroke information from said emitted signal and local storage for storing said detected stroke information, in association with the unique identifier of said writing medium.

Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.

Abstract: The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible.

Abstract: In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Abstract: To obtain a method for controlling power of a computer, a power control apparatus, and the computer which can prevent a user from feeling uneasy unnecessarily and inhibit a power-on problem from arising again. When the power switch is depressed, the power-on self test (POST) starts and if there is no error detected by that test in connection with the initialization of the IC, the operating system OS is loaded to make the computer operative (steps 200 through 208). If there is any error detected, a determination is made whether that error occurs as frequently as or more frequently than a predetermined number of times. If that error occurs as frequently as or more frequently than the predetermined number of times, an error indication is displayed and then the process ends. If that error occurs less frequently than the predetermined number of times, the error history is stored and then a setup for stabling the hardware operation is selected.

Abstract: In a liquid crystal device and a projection display device using the liquid crystal device as a light valve, for the purpose of preventing light incident from opposite the clear viewing direction from affecting the display, in a liquid crystal device (1), an optical center position (411) of a microlens (41) formed on a counter substrate (30) is offset toward the clear viewing direction as viewed from a center position (211) of a first opening area (21) formed for each pixel on the side of an active matrix substrate (20). For this reason, light incident on the counter substrate (30) from the direction inclined in the clear viewing direction is emitted from the active matrix substrate (20); however, light incident from the direction inclined opposite to the clear viewing direction that causes the degradation of contrast is not emitted from the active matrix substrate (20) and does not affect the display.

Abstract: In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Abstract: In a semiconductor device having a plurality of memory cells, each of the memory cells includes a floating gate, a control gate, a source and drain, and a silicide layer. The floating gate is formed on a semiconductor substrate of a first conductivity type through a gate insulating film to be insulated from a surrounding portion. The control gate is formed on the floating gate through an ONO film. The source and drain are formed on the semiconductor substrate on two sides of the floating gate and doped with an impurity of a second conductivity type. The silicide layer is formed on a surface of at least one of the drain and source. A method of manufacturing the semiconductor device is also disclosed.

Abstract: The invention provides an electrooptic device that can include a first substrate on which pixel electrodes, first thin film transistors electrically connected to the pixel electrodes, and scanning lines and data lines electrically connected to the first thin film transistors are formed, a second substrate opposing the first substrate and having a common electrode, and an electrooptic substance held between the first substrate and the second substrate. The electrooptical device can further include a switching element for discharging in capacitors constituted by the pixel electrodes on the first substrate, the electrooptic substance, and the common electrode on the second substrate. The invention makes it possible to remove charges from inside the electrooptic device.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: There are provided a material for a tension type color-selective device for a color cathode-ray tube, the material consisting essentially, by mass, of 0.1 to 1.0% Mo, from 0 but less than 0.01% W, from 0 but less than 0.2% Cr, less than 0.05% C, and the balance substantially Fe, the material having a half-width not less than 0.2 of a diffraction peak obtained regarding a (211) plane of the material in a X-ray diffraction by use of a Co-K&agr;1 ray, and a method of producing the material.

Abstract: A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacity formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacity which is formed on a third interlayer insulation film covering the bit line; a capacity contact which is formed through the third and second interlayer insulation film and makes a connection between the capacity and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.

Abstract: A manufacturing method of a semiconductor device having a CMOS logic circuit portion and a DRAM portion mixedly mounted on one chip. Preferably, the DRAM portion has a cylinder structure capacitor element. In the manufacturing method, the polysilicon film is formed on an interlayer film and on an inner wall of a cylinder-shaped opening formed in the interlayer film. Spherical or hemispherical grains called HSG are formed on the polysilicon film. The polysilicon film and the HSG on an upper surface of the interlayer film are removed while the polysilicon film and the HSG on the inner wall of the cylinder is retained. By performing these steps in this order, the HSG is reliably formed on the inner wall of the cylinder without fail. Therefore, a miniaturized capacitor element having high capacitance may be formed in a semiconductor device with a CMOS logic circuit portion and a DRAM portion mixedly mounted on one chip.