Patents by Inventor Ken Inoue

Ken Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020052706
    Abstract: To obtain a method for controlling power of a computer, a power control apparatus, and the computer which can prevent a user from feeling uneasy unnecessarily and inhibit a power-on problem from arising again. When the power switch is depressed, the power-on self test (POST) starts and if there is no error detected by that test in connection with the initialization of the IC, the operating system OS is loaded to make the computer operative (steps 200 through 208). If there is any error detected, a determination is made whether that error occurs as frequently as or more frequently than a predetermined number of times. If that error occurs as frequently as or more frequently than the predetermined number of times, an error indication is displayed and then the process ends. If that error occurs less frequently than the predetermined number of times, the error history is stored and then a setup for stabling the hardware operation is selected.
    Type: Application
    Filed: January 12, 2001
    Publication date: May 2, 2002
    Inventors: Shigefumi Odaohhara, Arimasa Naitoh, Ken Inoue
  • Publication number: 20020049722
    Abstract: A computing system includes a companion computing device having a display and a controller for transmitting a request to a host computing device; a host computing device for providing a user interface element and language support to the companion computing device; and a communication link for providing a bi-directional communication channel between the companion computing device and the host computing device.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 25, 2002
    Applicant: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20020041271
    Abstract: The present invention pertains to an input system for inputting information from a user, the input device system including at least one sheet of a writing medium having a unique identifier located thereon, a stylus input device for writing on the writing medium and emitting one or more signals, a detector for detecting said unique page identifier and stroke information from said emitted signal and local storage for storing said detected stroke information, in association with the unique identifier of said writing medium.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 11, 2002
    Applicant: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20020042888
    Abstract: The present invention pertains to a computing system having an input system with local storage interfaced with a computing device, wherein input information is transferred from the digitizer input system to the interfaced computing device based on an adaptive transfer policy that extends the battery life of the interfaced computing device. The interfaced computing device may be a PC. The digitizer input system can support automated, selective transfer policies based on the power management configuration of the PC interfaced with the digitizer input system and user-selected transfer policies.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 11, 2002
    Applicant: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20020040817
    Abstract: A computing system includes a handwriting input device and a computing device, the handwriting input device including an electronic pen input device having a first tip that emits a signal having a first characteristic and second tip that emits a signal having second characteristic; a detector for detecting the characteristic of the emitted signal; and a controller, interfaced with the computing device, for selectively interpreting the emitted signal as handwriting or as control information for the computing device based on the detected characteristic of the emitted signal.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 11, 2002
    Applicant: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20020041290
    Abstract: This invention pertains to a computing system and method for extending the graphical user interface (GUI) metaphor of a computing system to the physical realm to incorporate physical paper input into a graphical user interface (GUI). The system includes a computing device input system for recording a physical writing using an input pen and, responsive to a user's input, for selecting a region of said recorded physical writing, an object creation manager device for creating a object representation of the selected region of the recorded physical writing, and an object support component of said GUI for supporting use of said created object representation by said GUI.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 11, 2002
    Applicant: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20020003276
    Abstract: In a semiconductor device having a plurality of memory cells, each of the memory cells includes a floating gate, a control gate, a source and drain, and a silicide layer. The floating gate is formed on a semiconductor substrate of a first conductivity type through a gate insulating film to be insulated from a surrounding portion. The control gate is formed on the floating gate through an ONO film. The source and drain are formed on the semiconductor substrate on two sides of the floating gate and doped with an impurity of a second conductivity type. The silicide layer is formed on a surface of at least one of the drain and source. A method of manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: August 9, 2001
    Publication date: January 10, 2002
    Applicant: NEC Corporation
    Inventors: Ken Inoue, Hiroshi Sugawara
  • Patent number: 6316362
    Abstract: Disclosed herein is a method for manufacturing a semiconductor device having a high melting point metal silicide layer, especially a cobalt silicide layer. The uniformity of the metal silicide layer improves characteristics of the semiconductor device such as a heat resistance. In the present invention, the uniformity of the eventual metal silicide layer is improved by adjusting the degree of ion-implantation and thermal treatment of a precursor of the metal silicide layer.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Ken Inoue
  • Patent number: 6309515
    Abstract: There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm2.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventors: Ken Inoue, Hitoshi Abiko, Minoru Higuchi
  • Patent number: 6232224
    Abstract: A method of manufacturing a semiconductor device having a reliable contact structure. In this method, a semiconductor element such as a MOS transistor is formed on a semiconductor substrate. A first insulating film is formed on the semiconductor substrate so as to cover the semiconductor element and the first insulating film is selectively removed to form an opening. A stopper film is formed on at least a portion of an inner side surface of the opening. A contact surface of the semiconductor element exposed at a bottom portion of the opening is cleaned by wet etching which uses dilute hydrofluoric acid. The stopper film is made of material which is hard to be etched by dilute hydrofluoric acid. Then, the opening is filled with conductive material. In the cleaning process, the inner side surface of the contact hole is not etched and an inner diameter or a cross sectional area of the contact hole is not enlarged.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: May 15, 2001
    Assignee: NEC Corporation
    Inventor: Ken Inoue
  • Patent number: 6221764
    Abstract: After a cobalt film 12 and a titanium nitride film 13 as a barrier film against oxygen are formed over the surfaces of impurity diffusion layers 9, 10 on a silicon substrate 1, a first heat treatment is performed at a temperature below 400° C., forming a Co2Si film 31. Following this, the titanium nitride film and the unreacted cobalt film are removed, using a mixed solution of sulfuric acid and hydrogen peroxide and then another heat treatment is performed at a temperature in a range of 700˜900° C. and thereby forms a CoSi2 film. According to the present invention, the generation of spikes of cobalt silicide which may pierce the diffusion layers is well suppressed and, thus, the leakage current is well-controlled so that good transistor characteristics as well as high reliability are attained.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Ken Inoue
  • Patent number: 6211059
    Abstract: A semiconductor device is manufactured in accordance with the following steps. A prospective lower interconnection layer is formed on a substrate, and is patterned to form a lower interconnection. A first nitride film is formed on the entire surface. A first interlevel insulating film is formed on the entire surface of the first nitride film. A prospective upper interconnection layer is formed on the first interlevel insulating film, and is patterned to form an upper interconnection. A second nitride film is formed on the entire surface. The second nitride film is removed by patterning where a contact reaching the lower interconnection is to be formed. A second interlevel insulating film is formed on the entire surface. A plurality of contact holes are formed simultaneously to have different depths and reach the first and second nitride films respectively formed on the lower and upper interconnections.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: April 3, 2001
    Assignee: NEC Corporation
    Inventors: Ken Inoue, Masayuki Hamada
  • Patent number: 6136699
    Abstract: In manufacturing a semiconductor device, a refractory metal silicide layer having a first phase structure is formed. In this case, the refractory metal silicide layer having the first phase structure may be formed during performing a deposition operation of a refractory metal, in a state in which a semiconductor substrate is heated. Instead, a refractory metal film may be first deposited in a vacuum state, and then a semiconductor substrate may be heated in the vacuum state to change the refractory metal film into said refractory metal silicide layer having a first phase structure. After the refractory metal silicide layer having the first phase structure is formed, heat treatment is performed to change said refractory metal silicide layer having said first phase structure into a refractory metal silicide layer having a second phase structure.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: October 24, 2000
    Assignee: NEC Corporation
    Inventor: Ken Inoue
  • Patent number: 6114765
    Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in, the form of a substitutional solid solution.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
  • Patent number: 6084215
    Abstract: A temperature measuring unit of a wafer chuck measures the temperature of a wafer chuck when the wafer chuck holding a wafer W making in-unison contact with a contactor is made to contact a bottom jacket and the bottom jacket controls the wafer W to a specific test temperature. At least three recessed sections are formed in the back of the wafer chuck in such a manner that they have a depth extending from the back of the chuck to the vicinity of its surface. Through holes corresponding to the recessed sections are made in the bottom jacket. Temperature sensors that can be inserted into the through holes and in the recessed sections are provided on the side opposite to the wafer chuck of the bottom jacket. The sensors are supported by springs. During a test, the tips of the temperature sensors are caused to make elastic contact with the recessed sections.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: July 4, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Kunihiro Furuya, Toshihiro Yonezawa, Ken Inoue, Yoichi Nakagomi
  • Patent number: 6069045
    Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: May 30, 2000
    Assignee: NEC Corporation
    Inventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
  • Patent number: 5950083
    Abstract: A method for fabricating a CMOS transistor having a salicide structure is disclosed. A naturally formed oxide film covering surfaces of polycrystalline silicon film patterns, a P-type diffusion layer and an N-type diffusion layer is removed. Then, by introducing at least a titanium tetrachloride gas and a hydrogen gas into an electron cyclotron resonance plasma excited chemical vapor deposition system using microwaves (or into a plasma excited chemical vapor deposition system using helicon waves), titanium/silicide films are selectively formed on surfaces of the polycrystalline silicon film patterns and the P-type diffusion layer and the N-type diffusion layer. The crystal structure of the titanium/silicide films is of a C54 structure. During the formation of the titanium/silicide film, it is possible to suppress the occurrence of bridging and condensation phenomena.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventors: Ken Inoue, Makoto Sekine
  • Patent number: 5937300
    Abstract: A polysilicon film is deposited on a semiconductor substrate. A PSG film that can be removed from a material that composes field oxide films and sidewalls of a side surface portion of a gate electrode with a satisfactory selective ratio is deposited on the resultant semiconductor substrate. After the deposited films are processed as a gate electrode, the sidewalls are formed on the side surface portion of the gate electrode. Thereafter, the PSG film is selectively removed and the front surface of the polysilicon film, which composes the gate electrode, is exposed. Tungsten films are deposited on the front surfaces of the polysilicon film and source and drain region formed on the semiconductor substrate. After the SiON film is formed on the resultant semiconductor substrate, contact holes and then contacts are formed on the SiON film.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: August 10, 1999
    Assignee: NEC Corporation
    Inventors: Makoto Sekine, Hidenobu Miyamoto, Ken Inoue
  • Patent number: 5880505
    Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
  • Patent number: 5780361
    Abstract: An improved salicide process for selectively forming a monocobalt disilicide film on a substrate having a surface including both an insulation region containing silicon and a silicon region comprises the following steps. Cobalt is deposited on the substrate, wherein the substrate is heated up and maintained at a first temperature which is capable of causing cobalt to react only with silicon in the silicon region without reacting with silicon in the insulation region. The substrate is subjected to a vacuum annealing at a temperature equal to or near the first temperature to form a film made of one selected from the group consisting of dicobalt monosilicide and monocobalt monosilicide.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: July 14, 1998
    Assignee: NEC Corporation
    Inventor: Ken Inoue