Patents by Inventor Kenichi Kuroda

Kenichi Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 7336535
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 26, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • DATA LINE DISTURBANCE FREE MEMORY BLOCK DIVIDED FLASH MEMORY AND MICROCOMPUTER HAVING FLASH MEMORY THEREIN
    Publication number: 20080028134
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 31, 2008
    Inventors: Kiyoshi MATSUBARA, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Patent number: 7295476
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: November 13, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Semiconductor device and a method of manufacturing the same and designing the same
    Publication number: 20070222080
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: May 24, 2007
    Publication date: September 27, 2007
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Semiconductor integrated circuit device
    Publication number: 20070171692
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: March 28, 2007
    Publication date: July 26, 2007
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Publication number: 20070133308
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Application
    Filed: January 25, 2007
    Publication date: June 14, 2007
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Semiconductor integrated circuit device
    Patent number: 7212425
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: May 1, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Patent number: 7184321
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: February 27, 2007
    Assignees: Hitachi Ulsi Systems Co., Ltd., Renesas Technology Corp.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Semiconductor integrated circuit device
    Patent number: 7166893
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: January 23, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Semiconductor device and a method of manufacturing the same and designing the same
    Publication number: 20060202282
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: May 10, 2006
    Publication date: September 14, 2006
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Semiconductor integrated circuitry and method for manufacturing the circuitry
    Patent number: 7081649
    Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: July 25, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
  • Semiconductor device and a method of manufacturing the same and designing the same
    Patent number: 7071560
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: July 4, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Semiconductor integrated circuit device and a methodof manufacturing the same
    Publication number: 20060138568
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Application
    Filed: February 23, 2006
    Publication date: June 29, 2006
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Semiconductor device and a method of manufacturing the same
    Patent number: 7067888
    Abstract: Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits of the next stage of an I/O buffer circuit.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: June 27, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Aono, Kousuke Okuyama, Kozo Watanabe, Kenichi Kuroda
  • Semiconductor device
    Publication number: 20060118812
    Abstract: A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 ?m or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm?2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm?2.
    Type: Application
    Filed: June 2, 2005
    Publication date: June 8, 2006
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Ohtsuka, Yoichiro Tarui, Yoshinori Matsuno, Kenichi Kuroda, Hiroshi Sugimoto
  • Semiconductor integrated circuit device
    Patent number: 7002830
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: February 21, 2006
    Assignees: Renesas Technology Corp., Hitachi VLSI Engineering Corp.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Publication number: 20060034129
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 16, 2006
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Patent number: 6999350
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: February 14, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Antimicrobial copolymers and uses thereof
    Publication number: 20060024264
    Abstract: The present invention discloses random copolymers and methods of their use, including use of the copolymers as antimicrobial agents in pharmaceutical and non-pharmaceutical applications. The present invention also discloses compositions of the copolymers, and methods of preparing the copolymers.
    Type: Application
    Filed: July 22, 2005
    Publication date: February 2, 2006
    Inventors: Kenichi Kuroda, William DeGrado
  • Semiconductor integrated circuit device
    Publication number: 20060018172
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: September 19, 2005
    Publication date: January 26, 2006
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida