Patents by Inventor Kenichi Kuroda

Kenichi Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon
    Patent number: 6908837
    Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Semiconductor integrated circuitry and method for manufacturing the circuitry
    Publication number: 20050017274
    Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.
    Type: Application
    Filed: August 18, 2004
    Publication date: January 27, 2005
    Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
  • Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
    Publication number: 20040268025
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Application
    Filed: July 26, 2004
    Publication date: December 30, 2004
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
    Patent number: 6815778
    Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Koichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
  • Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
    Patent number: 6815748
    Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Koichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
  • Method for manufacturing a printed board on which a semiconductor device having two modes is mounted
    Patent number: 6804152
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: October 12, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Semiconductor integrated circuitry and method for manufacturing the circuitry
    Patent number: 6800888
    Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: October 5, 2004
    Assignees: Hitchi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
  • Semiconductor device and a method of manufacturing the same and designing the same
    Publication number: 20040152243
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
    Publication number: 20040150053
    Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Koichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
  • Semiconductor integrated circuit device and method of manufacturing the same
    Patent number: 6770527
    Abstract: In a DRAM having information storage capacitative elements over their corresponding bit lines BL, wiring grooves are defined in an insulating film for wire or interconnection formation, which are formed over a gage electrode serving as word lines of the DRAM. Sidewall spacers are formed on their corresponding side walls of the wiring grooves. Each bit line BL and a first layer interconnection composed of a tungsten film are formed so as to be embedded in the wiring grooves whose intervals are respectively narrowed by the sidewall spacers. The bit lines BL are respectively connected to a semiconductor substrate through connecting plugs. The bit lines BL and the connecting plugs are respectively connected to one another at the bottoms of the wiring grooves.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Kenichi Kuroda
  • SEMICONDUCTOR INTEGRATED CIRCUITRY AND METHOD FOR MANUFACTURING THE CIRCUITRY
    Publication number: 20040147077
    Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
  • Semiconductor integrated circuit device
    Patent number: 6751138
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 15, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Semiconductor integrated circuitry and method for manufacturing the circuitry
    Patent number: 6743673
    Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: June 1, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
  • Semiconductor integrated circuit device
    Publication number: 20040090838
    Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 13, 2004
    Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
  • Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
    Patent number: 6703667
    Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: March 9, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Koichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
  • Semiconductor device with an active region and plural dummy regions
    Patent number: 6693315
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: February 17, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Microcomputer including a flash memory that is two-way programmable
    Patent number: 6690603
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: February 10, 2004
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 6677194
    Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
  • Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
    Publication number: 20030197213
    Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
    Type: Application
    Filed: May 21, 2003
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Koichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
  • Semiconductor integrated circuit device and a method of manufacturing the same
    Publication number: 20030151109
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Application
    Filed: September 23, 2002
    Publication date: August 14, 2003
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto