Patents by Inventor Kenichiro Yoshii

Kenichiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220156182
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Patent number: 11307797
    Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 11269766
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20220035702
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Application
    Filed: October 5, 2021
    Publication date: February 3, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Shinichi KANNO
  • Patent number: 11169875
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Shinichi Kanno
  • Publication number: 20210296298
    Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Inventors: Tomoya SANUKI, Keisuke NAKATSUKA, Hiroshi MAEJIMA, Kenichiro YOSHII, Takashi MAEDA, Hideo WADA
  • Publication number: 20210240352
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tetsuya SUNATA, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 11023132
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Publication number: 20210118898
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
  • Publication number: 20210081120
    Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 18, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Daisuke IWAI, Kenichiro YOSHII, Tetsuya SUNATA
  • Publication number: 20210072923
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Daisuke IWAI, Tetsuya SUNATA
  • Patent number: 10936203
    Abstract: A memory device can be connected to a host through an interface. The memory device includes a nonvolatile memory which includes a plurality of blocks, and a controller which is electrically connected to the nonvolatile memory. In a case where a read command is received from the host, the controller reads first data designated by the read command from a first block of the nonvolatile memory, to transmit the first data to the host, and to write the first data to a second block of the nonvolatile memory instead of the first block.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 10892269
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • Patent number: 10891061
    Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Iwai, Kenichiro Yoshii, Tetsuya Sunata
  • Patent number: 10871920
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Daisuke Iwai, Tetsuya Sunata
  • Publication number: 20200379901
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Publication number: 20200334145
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Tetsuya Sunata, Daisuke Iwai
  • Patent number: 10783072
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20200264805
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Application
    Filed: September 5, 2019
    Publication date: August 20, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Shinichi KANNO
  • Patent number: 10747663
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Tetsuya Sunata, Daisuke Iwai