Patents by Inventor Kenji Iida

Kenji Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6343537
    Abstract: A piston 14 for sliding in a cylinder 12, a rod 16 of the piston 14, and a sleeve 15 fitted over the rod 16 and passing through a rod hole 13 of the cylinder are provided. A lock portion 18 is provided to an outer periphery of a tip end portion of the rod 16. The sleeve 15 having an outer peripheral face for airtightly sliding in the rod hole 13 in the cylinder 12 and an inner peripheral face for airtightly sliding on an outer peripheral face of the rod 16 is provided with an engaging portion 22 on an inner end side to be engaged with an inside of the rod hole 13 of the cylinder and an engaging portion 23 at an outer end side to be engaged with the lock portion 18 of the rod 16. Supply/discharge ports 18A and 19A for supplying and discharging pressure fluid to and from pressure chambers 18 and 19 on opposite sides of the piston 14 in the cylinder are provided and intermediate stop is possible by supplying and discharging pressure fluid to and from the ports.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: February 5, 2002
    Assignee: SMC Corporation
    Inventors: Kenji Iida, Akihiro Hirano
  • Publication number: 20010015008
    Abstract: A process for fabricating thin multi-layer circuit boards which allow the electrical conduction of remodeling pads to be easily cut do not use etching for gold, avoid the lift-off method for forming a thin chromium film on the wiring pattern layer, allow a defective wiring pattern layer to be removed, and which uses uniform heating of the substrate, from the back side thereof, at the time of pre-baking. A barrier metal (60) is excluded from a portion where the electrical conduction of a remodeling pad (62b) is to be cut (FIGS. 1 to 16). Alternatively, gold-plating resist is formed in order to avoid the etching for gold (FIGS. 17 to 19). Alternatively, a thin chromium film is formed in advance by etching on the wiring pattern layer (FIGS. 27 to 33). Alternatively, a metallic barrier film (122) is formed on each of the wiring pattern layers so that the wiring pattern layer can be removed without affecting other wiring pattern layers (FIGS. 36 to 42).
    Type: Application
    Filed: December 1, 2000
    Publication date: August 23, 2001
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Publication number: 20010013646
    Abstract: In conventional semiconductor devices, customarily, it is sought to position the mounting region of a semiconductor element in the center of a package, and hence the dimensions of the package are increased unnecessarily, but the object of the present invention is to avoid unnecessary increasing of the package dimensions, without impairing the required functions of the semiconductor device.
    Type: Application
    Filed: February 6, 2001
    Publication date: August 16, 2001
    Inventors: Atsunori Kajiki, Kenji Iida
  • Patent number: 6184476
    Abstract: A thin multi-layer circuit board having alternately stacked wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate. The wiring pattern layers are electronically connected through vias in the insulating layers to form a predetermined circuit pattern by said wiring pattern layers. A metallic barrier layer is formed on the top wiring pattern layer, except at an exclusion zone of the metallic barrier layer. An electronic part-mounting pad layer and a remodeling pad layer are formed on the metallic barrier layer. The remodeling pad layer is arranged adjacent the electronic part-mounting pad layer, with the exclusion zone therebetween.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Ltd.
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Patent number: 5839348
    Abstract: A cylinder apparatus includes a base plate, a piston fixed to the base plate and having a piston head and a piston rod connected thereto, a cylinder body having a cylinder chamber defined on one side of the piston head and a cylinder chamber defined on another side of the piston head around the piston rod, the cylinder body being supported for reciprocating movement with respect to the base plate in axial directions of the piston, an upper plate fixed to the cylinder body, and a bushing held in slidable contact with an outer circumferential wall surface of the cylinder body for guiding the reciprocating movement of the cylinder body.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: November 24, 1998
    Assignees: SMC Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Iida, Shuji Ono, Ken Kobayashi
  • Patent number: 5679268
    Abstract: A process for fabricating thin multi-layer circuit boards which allow the electrical conduction of remodeling pads to be easily cut do not use etching for gold, avoid the lift-off method for forming a thin chromium film on the wiring pattern layer, allow a defective wiring pattern layer to be removed, and which uses uniform heating of the substrate, from the back side thereof, at the time of pre-baking. A barrier metal (60) is excluded from a portion where the electrical conduction of a remodeling pad (62b) is to be cut (FIGS. 1 to 16). Alternatively, gold-plating resist is formed in order to avoid the etching for gold (FIGS. 17 to 19). Alternatively, a thin chromium film is formed in advance by etching on the wiring pattern layer (FIGS. 27 to 33). Alternatively, a metallic barrier film (122) is formed on each of the wiring pattern layers so that the wiring pattern layer can be removed without affecting other wiring pattern layers (FIGS. 36 to 42).
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: October 21, 1997
    Assignee: Fujitsu Limited
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Patent number: 5669283
    Abstract: A cylinder apparatus includes a base plate, a piston fixed to the base plate and having a piston head and a piston rod connected thereto, a cylinder body having a cylinder chamber defined on one side of the piston head and a cylinder chamber defined on another side of the piston head around the piston rod, the cylinder body being supported for reciprocating movement with respect to the base plate in axial directions of the piston, an upper plate fixed to the cylinder body, and a bushing held in slidable contact with an outer circumferential wall surface of the cylinder body for guiding the reciprocating movement of the cylinder body.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: September 23, 1997
    Assignees: SMC Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Iida, Shuji Ono, Ken Kobayashi
  • Patent number: 5415920
    Abstract: A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: May 16, 1995
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Satoh, Kenji Iida
  • Patent number: 5378310
    Abstract: A method of forming a conductive pattern layer structure includes providing an insulating member containing polyimide, forming a patterned thin film on the insulating member, and forming a patterned conductive layer on the thin film. The patterned conductive layer contains copper. Further, a barrier layer can be patterned to cover an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: January 3, 1995
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Satoh, Kenji Iida
  • Patent number: 5284696
    Abstract: A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: February 8, 1994
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Satoh, Kenji Iida
  • Patent number: 4725936
    Abstract: A DC-DC converter converts a DC input to a predetermined high-voltage DC output according to a predetermined control signal. An output unit has a pair of high- and low-voltage-side output paths and supplies the predetermined high-voltage DC output to a load. An output variation detecting unit has a resistor voltage dividing circuit including high- and low-voltage-side resistors connected in series between the pair of output paths and detects a variation in predetermined high-voltage DC output that follows a variation in the load. An inner shield shields the exterior of the resistor voltage dividing circuit. The inner shield is electrically connected to a node of the high- and-low voltage-side resistors. An outer shield shields the exterior of the inner shield. The outer shield is electrically connected to the low voltage-side output path of the pair of output paths.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: February 16, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Nakajima, Masayasu Doi, Kenji Iida
  • Patent number: D369610
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: May 7, 1996
    Assignee: SMC Corporation
    Inventor: Kenji Iida
  • Patent number: D376603
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: December 17, 1996
    Assignee: SMC Corporation
    Inventor: Kenji Iida
  • Patent number: D382331
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: August 12, 1997
    Assignee: SMC Kabushiki Kaisha
    Inventors: Kenji Iida, Takayuki Sawada
  • Patent number: D382631
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: August 19, 1997
    Assignee: SMC Kabushiki Kaisha
    Inventors: Kenji Iida, Takayuki Sawada