Patents by Inventor Kenji Imanishi

Kenji Imanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9502525
    Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 22, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura, Kenji Imanishi
  • Patent number: 9476435
    Abstract: A braking actuator uses a single cylinder without using a spring to achieve a 3-position operation. A partition plate and an intermediate check plate are affixed within a cylinder at suitable intervals in the axial direction. Inserted movably in the axial direction of the cylinder are a first piston disposed between a pressing lid and the intermediate check plate, a second piston disposed between the intermediate check plate and the partition plate, and a third piston disposed between the partition plate and a pressing lid. A rod which is axially movable within the cylinder has a base end attached to the third piston and a tip end which extends outside from the cylinder through the partition plate, the second piston, the intermediate check plate, the first piston, and the pressing lid. A stopper affixed to a middle portion of the rod moves the first piston or the second piston.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: October 25, 2016
    Assignee: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Hiroyuki Yamaguchi, Yozo Okuda, Koken Yanagido, Kenji Imanishi
  • Publication number: 20160258476
    Abstract: A crankshaft includes: journals that define a central axis of rotation; crank pins that are eccentric with respect to the journals; and crank arms for connecting the journals and the crank pins, wherein each of the crank arms or at least one of the crank arms integrally includes a counterweight. The crank arms have a recess in a surface adjacent to a corresponding one of the journals, the recess disposed inward of a peripheral region along a periphery of the surface, the recess disposed along the peripheral region. With this configuration, it is possible to provide a crankshaft which has reduced weight and increased torsional rigidity in combination with increased flexural rigidity.
    Type: Application
    Filed: October 14, 2014
    Publication date: September 8, 2016
    Inventors: Koichiro ISHIHARA, Kenji IMANISHI, Ken YOSHINO, Kunihiro YABUNO
  • Patent number: 9354047
    Abstract: A rotational misalignment between semiconductor wafers constituting a bonded wafer is calculated. A light source is arranged at a position which is on a front side of an opening of a notch and which is separated from an outer edge portion of a bonded wafer by a predetermined interval, and outputs light to irradiate the outer edge portion of the bonded wafer including the notch. A camera receives and photoelectrically converts reflected light that is specularly-reflected by the outer edge portion of the bonded wafer including the notch among the light outputted by the light source in order to output a brightness distribution of the reflected light as an image. A computer analyzes positions of notches from the image outputted by the camera to obtain a notch position misalignment, and further calculates a rotational misalignment between semiconductor wafers using a center position misalignment between the semiconductor wafers.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 31, 2016
    Assignees: KOBE STEEL, LTD., KOBELCO RESEARCH INSTITUTE, INC.
    Inventors: Masato Kannaka, Masakazu Kajita, Eiji Takahashi, Yuji Yamamoto, Masaru Akamatsu, Kunio Iba, Kenji Imanishi
  • Publication number: 20150330418
    Abstract: A braking actuator uses a single cylinder without using a spring to achieve a 3-position operation. A partition plate and an intermediate check plate are affixed within a cylinder at suitable intervals in the axial direction. Inserted movably in the axial direction of the cylinder are a first piston disposed between a pressing lid and the intermediate check plate, a second piston disposed between the intermediate check plate and the partition plate, and a third piston disposed between the partition plate and a pressing lid. A rod which is axially movable within the cylinder has a base end attached to the third piston and a tip end which extends outside from the cylinder through the partition plate, the second piston, the intermediate check plate, the first piston, and the pressing lid. A stopper affixed to a middle portion of the rod moves the first piston or the second piston.
    Type: Application
    Filed: February 12, 2014
    Publication date: November 19, 2015
    Inventors: Hiroyuki YAMAGUCHI, Yozo OKUDA, Koken YANAGIDO, Kenji IMANISHI
  • Publication number: 20150300432
    Abstract: This eddy-current retarding device includes: a magnet holding member that is coaxially provided to a rotating shaft and holds plural permanent magnets in a circumferential direction; a brake member that includes paired disk portions disposed on both sides of the magnet holding member in the axial direction of the rotating shaft, a connecting portion that connects the paired disk portions, and an eddy-current generating portion that causes eddy current due to rotation of the permanent magnets, and this brake member being supported in a relatively rotatable manner with respect to the rotating shaft; and a friction brake that causes a friction member to press against the brake member at the time of braking to bring the brake member to a stop.
    Type: Application
    Filed: August 12, 2013
    Publication date: October 22, 2015
    Inventors: Hiroyuki YAMAGUCHI, Kenji IMANISHI, Yasutaka NOGUCHI, Takashi FUTABA
  • Publication number: 20150279956
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Publication number: 20150206935
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and an amorphous insulating film formed between the substrate and the compound semiconductor stacked structure.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 23, 2015
    Inventors: Norikazu NAKAMURA, Atsushi YAMADA, Shiro OZAKI, Kenji IMANISHI
  • Patent number: 8969159
    Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Patent number: 8963164
    Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Sanae Shimizu, Kenji Imanishi, Atsushi Yamada, Toyoo Miyajima
  • Patent number: 8912571
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Toshihide Kikkawa, Kenji Imanishi
  • Patent number: 8896022
    Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Patent number: 8866157
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Publication number: 20140091320
    Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a third semiconductor layer and a fourth semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode contacting and formed on the fourth semiconductor layer, wherein the third semiconductor layer is formed of a semiconductor material for attaining p-type on an area just under the gate electrode, and a concentration of silicon in the fourth semiconductor layer is higher than that in the second semiconductor layer.
    Type: Application
    Filed: August 16, 2013
    Publication date: April 3, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: NORIKAZU NAKAMURA, Atsushi Yamada, Tetsuro Ishiguro, JUNJI KOTANI, Kenji Imanishi
  • Publication number: 20140091364
    Abstract: An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.
    Type: Application
    Filed: August 1, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kenji IMANISHI, Atsushi YAMADA, Tetsuro ISHIGURO, Toyoo MIYAJIMA
  • Patent number: 8669592
    Abstract: A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Toyoo Miyajima, Kenji Imanishi, Atsushi Yamada, Norikazu Nakamura
  • Publication number: 20140038377
    Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kenji IMANISHI, Toshihide KIKKAWA
  • Patent number: 8581335
    Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20130256690
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Inventors: NORIKAZU NAKAMURA, SHIROU OZAKI, MASAYUKI TAKEDA, TOYOO MIYAJIMA, TOSHIHIRO OHKI, MASAHITO KANAMURA, KENJI IMANISHI, TOSHIHIDE KIKKAWA, KEIJI WATANABE
  • Publication number: 20130256682
    Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.
    Type: Application
    Filed: December 11, 2012
    Publication date: October 3, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura, Kenji Imanishi