Patents by Inventor Kenji Imanishi

Kenji Imanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020090789
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Application
    Filed: March 8, 2002
    Publication date: July 11, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Patent number: 6417519
    Abstract: A carrier transit layer made of group III-V compound semiconductor is formed on a semiconductor substrate. A carrier supply layer is formed on the carrier transit layer. The carrier supply layer supplies carriers for generating two-dimensional carrier gas in an interface between the carrier supply layer and carrier transit layer. The carrier supply layer is made of group III-V compound semiconductor which contains In as group III element. A gate electrode is disposed above a partial area of the carrier supply layer. An intermediate layer is disposed between the gate electrode and carrier supply layer. The intermediate layer is made of group III-V compound semiconductor not containing In as group III element. An ohmic electrode is disposed on both sides of the gate electrode.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: July 9, 2002
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Tsuyoshi Takahashi
  • Patent number: 6399971
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Publication number: 20020027232
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1-xAsySb1-y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Application
    Filed: November 13, 1998
    Publication date: March 7, 2002
    Inventors: HISAO SHIGEMATSU, KENJI IMANISHI, HITOSHI TANAKA
  • Publication number: 20020020592
    Abstract: A single row rotating-type eddy current braking apparatus for use with a rotor mounted on a powered shaft comprises a support ring, a plurality of magnets, a plurality of ferromagnetic switching plates, and a support body. The switching plates or magnets are capable of rotating with respect to each other to effect braking. The dimensions of the switching plates and angular displacement of the magnets and switching plates are controlled to minimize drag torque when in a non-braking state. The switching plates can be made to rotate and the bearing can be employed in combination with the rotating and stationary components to alleviate problems such as thermal expansion and wear. The apparatus also utilizes a pneumatic cylinder designed to rotate in the direction of the shaft rotation to achieve a braking state, and can employ a single rod double acting cylinder to switch between braking and non-braking states.
    Type: Application
    Filed: February 8, 2001
    Publication date: February 21, 2002
    Inventors: Yasunori Tani, Kenji Araki, Koichi Miura, Akira Saito, Yasutaka Noguchi, Kenji Imanishi, Keiichi Kawano
  • Patent number: 6034382
    Abstract: A current-driven-type semiconductor device including a substrate, an active part formed on the substrate, and a conductive semiconductor layer formed on the active part as a current path to the active part, wherein the conductive semiconductor layer includes a semiconductor layer having a first conductivity type and a first bandgap, and a semiconductor barrier layer having the first conductivity type and a second bandgap larger than the first bandgap.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventor: Kenji Imanishi
  • Patent number: 5856209
    Abstract: A method for fabricating a semiconductor device includes a step of depositing a first compound semiconductor layer by a MOVPE process to have a first conductivity type, doping a surface of the first compound semiconductor layer to the same, first conductivity type, by implementing a planar doping process as a result of decomposition of a gaseous dopant, such that no substantial growth of the first compound semiconductor layer occurs during the planar doping process, and depositing a second compound semiconductor layer of the first conductivity type on the doped surface of the first compound semiconductor layer by a MOVPE process.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: January 5, 1999
    Assignee: Fujitsu Limited
    Inventor: Kenji Imanishi
  • Patent number: 5682040
    Abstract: A method for fabricating a semiconductor device includes a step of depositing a first compound semiconductor layer by a MOVPE process to have a first conductivity type, doping a surface of the first compound semiconductor layer to the same, first conductivity type, by implementing a planar doping process as a result of decomposition of a gaseous dopant, such that no substantial growth of the first compound semiconductor layer occurs during the planar doping process, and depositing a second compound semiconductor layer of the first conductivity type on the doped surface of the first compound semiconductor layer by a MOVPE process.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: October 28, 1997
    Assignee: Fujitsu Limited
    Inventor: Kenji Imanishi
  • Patent number: 5610410
    Abstract: A field effect group III-V compound semiconductor device having a Schottky gate electrode includes: a semiconductor substrate; a plurality of group III-V compound semiconductor crystal layers including an active layer for transferring carriers and formed on the semiconductor substrate; an InAlP layer formed at least a partial surface of the group III-V compound semiconductor crystal layers; a gate electrode formed on the InAlP layer and forming Schottky contact therewith; and a pair of source/drain electrodes disposed to interpose therebetween the gate electrode, and forming ohmic contact with the active layer. A group III-V compound semiconductor device is provided with a Schottky electrode highly resistant to a current flow.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: March 11, 1997
    Assignee: Fujitsu Limited
    Inventor: Kenji Imanishi