Abstract: Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.

Abstract: Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.

Abstract: Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces.

Abstract: Methods and apparatuses to multiplex logic data pseudo synchronously are described. A representation of a multiplexer logic is generated to transmit data items asynchronously relative to a design clock. The data items may be transmitted under control of a transmission clock from a first integrated circuit to a second integrated circuit. A representation of a counter logic may be generated to couple with the multiplexer logic for transmitting the data asynchronously. Additionally, a representation of reset logic may be generated for a configuration to repeatedly reset the counter logic. Synchronization signals may be generated for a design clock cycle of a design clock driving the data items. The synchronization signals may be transmitted via the transmission clock asynchronous with the design clock.

Abstract: Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, using a second set of wiring resources in the representation, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size, from wiring resources in the first set. Other methods and systems for optimizing and/or designing ICs are also described, and machine-readable media containing executable program instructions which cause systems to perform one or more of these methods are also described.

Abstract: Methods and apparatuses to design a circuit. In one embodiment, the method includes determining a first multiplexing ratio by a computer. The method, in one embodiment, further includes determining, according to the first multiplexing ratio, a first partition solution of the circuit and a first trace assignment solution for nets crossing partition boundaries of the first partition solution of the circuit. In one embodiment, the first trace assignment solution time multiplexes signals for a first plurality of nets crossing partition boundaries of the first partition solution according to the first multiplexing ratio, the first trace assignment solution satisfying a trace constraint, the first partition solution satisfying an area constraint when circuitry for time multiplexing signals for the first plurality of nets is considered.

Abstract: Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a fewer quantity of time-shared instances of the logical block. The plurality of the instances in the first design is replaced with the fewer time-shared instances in the second design. The time-shared instances in the second design have elements to time multiplex the internal states.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.

Abstract: Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the list as well as a means for committing paths to the implementation if such paths are required for making the circuit implementation valid. Paths with worst case attributes are iteratively removed from the list until all paths in the list are committed to the implementation. Other methods and apparatuses are also described.

Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion.

Abstract: Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a fewer quantity of time-shared instances of the logical block. The plurality of the instances in the first design is replaced with the fewer time-shared instances in the second design. The time-shared instances in the second design have elements to time multiplex the internal states.

Abstract: Methods and apparatuses for designing logic are described. In one embodiment, a method includes determining a directive which specifies a format for data in a data processing operation and creating a representation of logic to perform the data processing operation, wherein the creating uses the directive as a minimum format, rather than an exact or required format, for at least a portion of the representation of logic. Other methods are disclosed, and systems and machine readable media are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

Abstract: Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second multiplexers. Another exemplary method includes decomposing a representation of a first multiplexer into a representation of a plurality of second multiplexers, which are coupled together at a common output without any intervening multiplexers between the second multiplexers and the common output, and partitioning the second multiplexers between portions of at least one integrated circuit.

Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Abstract: Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.

Abstract: Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.