Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

Abstract: Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred applications in automatic physical synthesis for RTL (register transfer level) netlist. In an embodiment, a reset conditioning circuit is inserted into the original integrated circuit to make the reset behavior more reliable to avoid unpredictable states, especially for the de-assertion state of the reset signal. The reset conditioning circuit can provide an asynchronous reset signal output with extended duration so that all the load registers employing asynchronous reset signal will get the reset properly. Further, the reset conditioning circuit can modify the timing of the reset signal so that its de-assertion edge is synchronized with a rising clock edge.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.

Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources.

Abstract: Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.

Abstract: Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.

Abstract: Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.

Abstract: Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.

Abstract: Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second multiplexers. Another exemplary method includes decomposing a representation of a first multiplexer into a representation of a plurality of second multiplexers, which are coupled together at a common output without any intervening multiplexers between the second multiplexers and the common output, and partitioning the second multiplexers between portions of at least one integrated circuit.

Abstract: Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology independent register transfer level (RTL) netlist, which is to be partitioned between multiple ICs. Based on the estimation, the RTL netlist is partitioned between the multiple ICs. In response to the partition and the estimation, immediate feedback information is provided to a user.