Abstract: One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of the delays caused by the TDM channel. The TDM channel is modeled with its equivalent delays. Thus, a transformation tool is allowed to take into account the original constraints and time budgeting of the sending subsystem and the receiving subsystem. The problem of asynchronous clock domains is eliminated; and, simulation time of the multiplexed circuit is also improved. In some embodiments of the present invention, multiple TDM slots are assigned to a particular signal to reduce the equivalent connection delay caused by the TDM channel for the particular signal.

Abstract: Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays).

Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.

Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.

Abstract: A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).

Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.

Abstract: Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.

Abstract: Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In one aspect of the present invention, a method to design a circuit includes: determining likelihood of a design constraint being violated in an implementation of a first circuit design (e.g., a technology specific netlist with or without a placement solution); and, modifying the first circuit design to reduce the likelihood of the design constraint being violated. In one example, the implementation of the first circuit design includes a routing solution for implementing the first circuit design; and, the first circuit is modified through sizing an instance of a logic element, buffering a signal, load shielding for a signal, or other operations.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays).

Abstract: A method is described that comprises determining a state machine design point from a plurality of state machine design point options. At least one of the plurality of state machine design point options corresponds to a safe design point. The method then further comprises, if the safe design point is the determined state machine design point, forming a safe state machine model. The safe state machine model has valid state logic separated from invalid state logic. Another method is described that comprises detecting an invalid state of a state machine with invalid state logic and setting a state machine register to a valid state with the invalid state logic. The method then further comprises continuing valid state operation of the state machine with valid state logic. The valid state logic is separated from the invalid state logic.

Abstract: An embodiment of the present invention includes a range generator to simplify equivalence checking. A range generator is constructed. The range generator is represented by a characteristic function of a range of a cut function for a cut circuit in an implementation circuit and a reference circuit. The range generator is simpler than the cut circuit. Equivalence of the implementation circuit and the reference circuit is checked using the range generator.

Abstract: Methods and apparatuses for designing an integrated circuit (IC). In one exemplary method, a hardware description language (HDL) code is compiled to produce a representation of logic, and a portion of this representation of logic is allocated to a first physical portion of an area of the IC. This portion is reallocated automatically, according to machine determined parameters, such that a modified portion of the representation is allocated to the first physical portion. Examples of this reallocating include moving logic between regions on the IC, replicating logic based on the regions of the IC, decomposing RTL instances into elements based on information concerning the regions, reducing logic path crossings of a region's boundaries, and assuring that the original allocation or the result of a reallocation can be accommodated by the first physical portion of the IC.

Abstract: A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).

Abstract: Methods and systems for designing integrated circuits. In one exemplary method, a first plurality of points in a first representation of a circuit are identified, and the first representation is modified to produce a second representation for which a second plurality of points are identified. The first representation is compared to the second representation at the first plurality and second plurality of points to determine whether the first representation is equivalent to the second representation. Other features and embodiments are also described.

Abstract: Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate primary inputs and outputs. When there are one or more unmatched registers between the first netlist and the second netlist, the unmatched registers are pushed to the primary inputs or outputs using retiming. At the primary inputs, a subspace generator is used to generate subspaces. The subspaces are used to identify non-equivalences between the first and second netlists. Other features and embodiments are also described.

Abstract: Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTh netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays). Other examples of methods and apparatuses are described.