Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.

Abstract: Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.

Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.

Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.

Abstract: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.

Abstract: Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.

Abstract: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.

Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.

Abstract: Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: Methods and apparatuses for automated synthesis transformation for carry save optimization and/or for the correction of dropped truncation after widening an adder. In one embodiment of the present invention, a correction input is automatically generated for a widened adder to correct the dropping or truncation of result bits that is performed by the adder before the widening. In one example the dropped result bits are part of the user's HDL specification. In another example the carry save optimization is enabled by a retiming operation. In one embodiment of the present invention, one or more logic operators between adders are pushed (e.g., forward or backward) across at least one of the adders so that the adders can be collapsed for carry save optimization. In one embodiment, an adder followed by a comparator is transformed to use a carry save adder followed by a comparator so that the carry chain in the original adder can be eliminated.

Abstract: Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces.

Abstract: Digital circuits with time multiplexed redundancy and methods and apparatuses for their automated designs generated from single-channel circuit designs. At least one embodiment of the present invention includes a digital circuit which detects or corrects transitory upsets through time-multiplexed resource sharing. In one embodiment of the present invention, time-multiplexed resource sharing is used to reduce the die area for implementing modular redundancy. One embodiment of the present invention automatically and efficiently synthesizes multi-channel hardware for time-multiplexed resource sharing by automatically generating a time-multiplexed design of multi-channel circuits from the design of a single-channel circuit, in which at least a portion of the channels are allocated for modular redundancy.

Abstract: Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In one aspect of the present invention, a method to design a circuit includes: determining likelihood of a design constraint being violated in an implementation of a first circuit design (e.g., a technology specific netlist with or without a placement solution); and, modifying the first circuit design to reduce the likelihood of the design constraint being violated. In one example, the implementation of the first circuit design includes a routing solution for implementing the first circuit design; and, the first circuit is modified through sizing an instance of a logic element, buffering a signal, load shielding for a signal, or other operations.

Abstract: One embodiment of the present invention determines equivalence between a first circuit and a second circuit. The first circuit represented by a first circuit function is decomposed into first and second decomposition circuits represented by first and second decomposition functions, respectively. The first circuit has a plurality of first primary inputs and first primary outputs. The plurality of the first primary inputs includes first and second primary input subsets. A reducing function of a reducing circuit is selected for the first decomposition function to reduce complexity of a first composition of the first circuit function and the reducing function. Equivalence is determined between the first composition with a second composition of the reducing function and a second circuit function of a second circuit. The second circuit has a plurality of second primary inputs and second primary outputs matching to the plurality of the first primary inputs and the first primary outputs, respectively.

Abstract: Methods and apparatuses to maintain and propagate statistical data during circuit synthesis. At least one embodiment of the present invention maintains and propagates statistical data during and after circuit synthesis transformation operations. In one example, the signal switching activity is calculated once at the RTL level and then propagated and/or maintained at various nodes of the circuit through the process of logic synthesis. Thus, the statistical analysis of entire circuit during or after the logic synthesis is avoided. In one example, power optimization is performed during logic synthesis. A portion of the logic synthesis transformation is driven by the power consumption optimization; and, the statistical data about circuit activity maintained at the nodes of the circuit during the synthesis process is used to calculate the power consumption at various points in the process of synthesis transformation.

Abstract: An embodiment of the present invention includes a range generator to simplify equivalence checking. A range generator is constructed. The range generator is represented by a characteristic function of a range of a cut function for a cut circuit in an implementation circuit and a reference circuit. The range generator is simpler than the cut circuit. Equivalence of the implementation circuit and the reference circuit is checked using the range generator.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.