Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: A two-terminal device comprises a bottom electrode. A device element is formed upon the bottom electrode. The two-terminal device also comprises a top electrode that is formed upon the device element. The bottom electrode and the top electrode are aligned. The bottom electrode and top electrode also have a same width and depth.

Abstract: Resistive memory devices are provided which are configured to mitigate resistance drift. A device comprises a phase-change element, a resistive liner, a first electrode, a second electrode, and a third electrode. The resistive liner is disposed in contact with a first surface of the phase-change element. The first electrode is coupled to a first end portion of the resistive liner. The second electrode is coupled to a second end portion of the resistive liner. The third electrode is coupled to the first surface of the phase-change element.

Abstract: Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

Abstract: A semiconductor structure includes a first electrode; a second electrode; a dielectric material between the first electrode and the second electrode, the dielectric material having at least one wall extending from the first electrode to the second electrode to define a void within the dielectric material and between the first electrode and the second electrode; and a layer of phase change material on the at least one wall of the dielectric material and in contact with the first electrode and the second electrode.

Abstract: A semiconductor structure comprises an active device stack comprising one or more layers, the one or more layers comprising a top electrode. The semiconductor structure also comprises an additional layer disposed over the active device stack, an encapsulation layer surrounding the active device stack and the additional layer, and a contact to the top electrode coupled to the additional layer.

Abstract: A semiconductor component includes a dielectric layer including an opening. The semiconductor component further includes a liner arranged in the opening in direct contact with the dielectric layer. The semiconductor component further includes a wetting layer arranged in the opening in direct contact with the liner. The semiconductor component further includes an interconnect structure arranged in the opening in direct contact with the wetting layer. The semiconductor component further includes a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: A phase change memory (PCM) cell having a mushroom configuration includes a first electrode, a heater electrically connected to the first electrode, a first projection liner electrically connected to the heater, a PCM material electrically connected to the first projection liner, a second electrode electrically connected to the PCM material, and a second projection liner electrically connected to the first projection liner and the second electrode.

Abstract: An apparatus includes a heater, a phase change material region, and a top metal layer. The phase change material region includes a doped GST layer and a first GST layer. The first GST layer is between the doped GST layer and the heater, and the doped GST layer is doped differently than the first GST layer. The phase change material region is positioned between the heater and the top metal layer.

Abstract: An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

Abstract: Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

Abstract: A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode.

Abstract: A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Abstract: A semiconductor structure includes a heater located in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner in direct contact with a top surface of the heater in a second layer of the device, a spacer disposed adjacent the PCM liner in the second layer of the device, and a PCM stack disposed above the PCM liner in the second layer of the device.

Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Abstract: A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Abstract: A heater, a system, and a method for linearly changing the resistance of the phase change memory through a graded heater. The system may include a phase change memory. The phase change memory may include a dielectric. The phase change memory may also include a heater patterned on the dielectric, the heater including: an outside conductive heating layer that has a higher resistance than other layers of the heater, and an inside conductive heating layer that has a lower resistance than the outside conductive heating layer, where the outside conductive heating layer is at an outside area of the heater and the inside conductive heating layer is at an inside area of the heater. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Abstract: A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

Abstract: A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element that is deposited on the intermediate electrode. The resistive RAM module also comprises a sink electrode that is in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element and the memristor element is electrically between the intermediate electrode and the sink electrode.