Patents by Inventor KHANG CHOONG YONG
KHANG CHOONG YONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955436Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.Type: GrantFiled: April 24, 2019Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song, Stephen Hall
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Publication number: 20230396030Abstract: High-speed, hermaphroditic electrical connectors may be connected to form a hermaphroditic connector assembly that uses less space than existing connector assemblies. A housing can provide a first and second engagement feature that are intended to engage each other so that when two such connectors are rotated 180 degrees the engagement features allow two such connectors to mate together. Cables can be connected directly to the terminals so as to provide for improved electrical performance.Type: ApplicationFiled: December 10, 2021Publication date: December 7, 2023Inventors: John C. Laurx, Khang Choong Yong, Michael D. Rost, Pue Xie
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Patent number: 11798894Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.Type: GrantFiled: June 25, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Kooi Chi Ooi, Min Suet Lim
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Patent number: 11729900Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.Type: GrantFiled: March 14, 2022Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
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Patent number: 11658127Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.Type: GrantFiled: June 27, 2019Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Eng Huat Goh, Jiun Hann Sir, Khang Choong Yong, Boon Ping Koh, Wil Choon Song, Min Suet Lim
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Patent number: 11652057Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.Type: GrantFiled: May 7, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Khang Choong Yong, Eng Huat Goh, Min Suet Lim, Robert Sankman, Telesphor Kamgaing, Wil Choon Song, Boon Ping Koh
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Patent number: 11614811Abstract: Methods and systems may provide for a gyratory sensing system (GSS) for extending the human machine interface (HMI) of an electronic device, particularly small form factor, wearable devices. The gyratory sensing system may include a gyratory sensor and a rotatable element to engage the gyratory sensor. The rotatable element may be sized and configured to be easily manipulated by hand to extend the HMI of the electronic device such that the functions of the HMI may be more accessible. The rotatable element may include one or more rotatable components, such as a body, edge or face of a smart watch, that each may be configured to perform a function upon rotation, such as resetting, selecting, and/or activating a menu item.Type: GrantFiled: October 7, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Khang Choong Yong, Will Choon Song, Howard L. Heck, Su Sin Florence Phun
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Patent number: 11552403Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.Type: GrantFiled: October 27, 2021Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Eng Huat Goh, Min Suet Lim, Boon Ping Koh, Wil Choon Song, Khang Choong Yong
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Publication number: 20220304143Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.Type: ApplicationFiled: March 14, 2022Publication date: September 22, 2022Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
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Patent number: 11422642Abstract: Methods and systems may provide for a gyratory sensing system (GSS) for extending the human machine interface (HMI) of an electronic device, particularly small form factor, wearable devices. The gyratory sensing system may include a gyratory sensor and a rotatable element to engage the gyratory sensor. The rotatable element may be sized and configured to be easily manipulated by hand to extend the HMI of the electronic device such that the functions of the HMI may be more accessible. The rotatable element may include one or more rotatable components, such as a body, edge or face of a smart watch, that each may be configured to perform a function upon rotation, such as resetting, selecting, and/or activating a menu item.Type: GrantFiled: March 8, 2021Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Khang Choong Yong, Wil Choon Song, Howard L. Heck, Su Sin Florence Phun
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Patent number: 11393760Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.Type: GrantFiled: September 15, 2020Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Boon Ping Koh, Eng Huat Goh, Jiun Hann Sir, Khang Choong Yong, Min Suet Lim, Wil Choon Song
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Publication number: 20220137726Abstract: Methods and systems may provide for a gyratory sensing system (GSS) for extending the human machine interface (HMI) of an electronic device, particularly small form factor, wearable devices. The gyratory sensing system may include a gyratory sensor and a rotatable element to engage the gyratory sensor. The rotatable element may be sized and configured to be easily manipulated by hand to extend the HMI of the electronic device such that the functions of the HMI may be more accessible. The rotatable element may include one or more rotatable components, such as a body, edge or face of a smart watch, that each may be configured to perform a function upon rotation, such as resetting, selecting, and/or activating a menu item.Type: ApplicationFiled: October 7, 2021Publication date: May 5, 2022Inventors: Khang Choong Yong, Will Choon Song, Howard L. Heck, Su Sin Florence Phun
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Patent number: 11304299Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.Type: GrantFiled: August 31, 2020Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
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Patent number: 11290059Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: GrantFiled: December 13, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Khang Choong Yong, Raymond Chong, Ramaswamy Parthasarathy, Stephen Hall, Chin Lee Kuan
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Patent number: 11277903Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.Type: GrantFiled: March 28, 2019Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
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Publication number: 20220052458Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 27, 2021Publication date: February 17, 2022Inventors: Eng Huat GOH, Min Suet LIM, Boon Ping KOH, Wil Choon SONG, Khang Choong YONG
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Patent number: 11211714Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.Type: GrantFiled: November 21, 2017Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Eng Huat Goh, Min Suet Lim, Boon Ping Koh, Wil Choon Song, Khang Choong Yong
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Publication number: 20210366883Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 2, 2021Publication date: November 25, 2021Applicant: Intel CorporationInventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
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Patent number: 11177226Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.Type: GrantFiled: June 24, 2019Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Bok Eng Cheah, Eng Huat Goh, Jackson Chung Peng Kong, Khang Choong Yong, Min Suet Lim
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Patent number: 11178768Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.Type: GrantFiled: April 1, 2016Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh