Patents by Inventor Khanh Nguyen

Khanh Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Determination of word line to word line shorts between adjacent blocks
    Patent number: 9514835
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: December 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Sagar Magia, Jagdish Sabde, Khanh Nguyen
  • Time domain ramp rate control for erase inhibit in flash memory
    Patent number: 9490020
    Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 8, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Kenneth Louie, Khanh Nguyen
  • Temperature and pH-sensitive block copolymer having excellent safty in vivo and hydrogel and drug delivery system using thereof
    Patent number: 9469728
    Abstract: Disclosed herein are pH- and temperature-sensitive block copolymer with excellent safety and a method for preparing the same and a hydrogel and a drug carrier using the block copolymer. According to the present invention, the pH- and temperature-sensitive block copolymer comprises: obtained by copolymerization of: (a) polyethylene glycol-based compound (A); and (b) poly (?-amino ester)-based oligomer (B) or poly (amido amine)-based oligomer (C) or coupling of mixture (D) thereof. In order to control biodegradation rate, the block copolymer is mixed with poly (amido amine)-based oligomer instead of the poly (?-amino ester)-based oligomer and then coupling them.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: October 18, 2016
    Assignee: SUNGKYUNKWAN UNIVERSITY FOUNDATION FOR CORPORATE
    Inventors: Doo Sung Lee, Minh Khanh Nguyen, Bong Sup Kim
  • AD HOC DIGITAL MULTI-DIE POLLING FOR PEAK ICC MANAGEMENT
    Publication number: 20160293264
    Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.
    Type: Application
    Filed: October 30, 2015
    Publication date: October 6, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
  • SYSTEM AND METHOD FOR CREATING AND TRANSITIONING TO MULTIPLE FACETS OF A SOCIAL MEDIA OBJECT IN A SOCIAL NETWORK
    Publication number: 20160283739
    Abstract: Systems and methods for facilitating users to create multi-faceted social media objects (e.g., text, images, videos, etc.) with one public facing front side and multiple secondary facets that have optional privacy controls are provided. Users can scroll down a feed and perform gestures on each social media object to transition them to flipsides to view optionally private content in an intuitive manner. Graphical animations for transitioning from the front side of the social media object to the secondary facets can be simultaneously viewed within the feed interface. This enables a user to create a publicly visible social media object and essentially hide a message on the flipside(s) for selected other users to access. The hidden message may be contextual to the public side.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 29, 2016
    Inventors: Stephen Hsu, Khanh Nguyen
  • Non-volatile memory with multi-word line select for defect detection operations
    Patent number: 9449694
    Abstract: A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: September 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia, Khanh Nguyen
  • TIME DOMAIN RAMP RATE CONTROL FOR ERASE INHIBIT IN FLASH MEMORY
    Publication number: 20160260488
    Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Inventors: Kenneth Louie, Khanh Nguyen
  • TECHNIQUES FOR PROGRAMMING OF SELECT GATES IN NAND MEMORY
    Publication number: 20160189778
    Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Applicant: SanDisk Technologies, Inc.
    Inventors: Hao NGUYEN, Man MUI, Khanh NGUYEN, Seungpil LEE, Toru ISHIGAKI, Yingda DONG
  • Time Domain Ramp Rate Control for Erase Inhibit in Flash Memory
    Publication number: 20160180939
    Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Kenneth Louie, Khanh Nguyen
  • Time domain ramp rate control for erase inhibit in flash memory
    Patent number: 9361990
    Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 7, 2016
    Assignee: SanDisk Technologies, Inc.
    Inventors: Kenneth Louie, Khanh Nguyen
  • Operational amplifier methods for charging of sense amplifier internal nodes
    Patent number: 9349468
    Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 24, 2016
    Assignee: SanDisk Technologies, Inc.
    Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
  • Biasing of unselected blocks of non-volatile memory to reduce loading
    Patent number: 9349458
    Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: May 24, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Kenneth Se Mon Louie, Khanh Nguyen
  • BIASING OF UNSELECTED BLOCKS OF NON-VOLATILE MEMORY TO REDUCE LOADING
    Publication number: 20160111161
    Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 21, 2016
    Inventors: Kenneth Se Mon Louie, Khanh Nguyen
  • Word line kick during sensing: trimming and adjacent word lines
    Patent number: 9318210
    Abstract: When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line's voltage is dropped briefly, can be applied to neighboring non-selected word lines.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: April 19, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: James V. Hart, Kenneth Louie, Khanh Nguyen, Man Mui
  • Techniques for programming of select gates in NAND memory
    Patent number: 9305648
    Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 5, 2016
    Assignee: SanDisk Technologies, Inc.
    Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
  • Non-Volatile Memory with Multi-Word Line Select for Defect Detection Operations
    Publication number: 20160071594
    Abstract: A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia, Khanh Nguyen
  • Operational Amplifier Methods for Charging of Sense Amplifier Internal Nodes
    Publication number: 20160055916
    Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
  • Techniques for Programming of Select Gates in NAND Memory
    Publication number: 20160055911
    Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
  • Method and system for a high availability framework
    Patent number: 9268662
    Abstract: A method for providing a high availability framework, comprises executing a first component of the high availability framework within a shared kernel based on a first operating system, executing a second component of the high availability framework within a first userland of the first operating system, and executing a third component of the high availability framework within a second userland of a second operating system, wherein the second operating system is an older version of the first operating system. The method further comprises monitoring, by a health service of the shared kernel, the first operating system and a first application executing within the first userland; and monitoring, by the health service, the second operating system and a second application executing within the second userland.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: February 23, 2016
    Assignee: Oracle International Corporation
    Inventors: Pramod Nagaraja Rao, Gia-Khanh Nguyen, Yue Lai
  • Determination of Word Line to Word Line Shorts Between Adjacent Blocks
    Publication number: 20160012904
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: Jagdish Sabde, Sagar Magia, Khanh Nguyen