Abstract: The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer.

Abstract: The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

Abstract: A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.

Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Abstract: Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.

Abstract: Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.

Abstract: Disclosed are systems and methods that employ a structural framework of cell gratings placed on a wafer surface during an immersion lithography process to restrict motion of the immersion fluid. Thus, when the stepper lens comes in contact with the immersion fluid, a typically stable immersion fluid dynamics can be maintained with the cells during the immersion lithography process. In addition, various monitoring and control systems are employed to regulate stability of the immersion fluid.

Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.

Abstract: Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Abstract: The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.

Abstract: Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.

Abstract: Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.

Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer.

Abstract: The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period.

Abstract: A system for performing inventory control for wafers, unpackaged integrated circuits and packaged integrated circuits is provided. The system includes barcode readers, sorters and transporters operable to locate and relocate wafers, unpackaged circuits and packaged circuits. The system further includes a feedback system for feeding back information generated by the barcode readers, sorters, transporters and/or manufacturing devices associated with the wafers, unpackaged circuits and packaged circuits. The system further provides for generating Electronic Data Interchange (EDI) data that can be transmitted to wafer suppliers and employed in controlling wafer ordering, purchasing, processing and returning.

Abstract: Systems and methods that improve process control in semiconductor manufacturing are disclosed. According to an aspect of the invention, conditions in a cluster tool environment and/or a wafer therein can be monitored in-situ via, for example, a scatterometry system, to determine whether parameters associated with wafer production are within control limits. A cluster tool environment can include, for example, a lithography track, a stepper, a plasma etcher, a cleaning tool, a chemical bath, etc. If an out-of-control condition is detected, either associated with a tool in the cluster tool environment or with the wafer itself, compensatory measures can be taken to correct the out-of-control condition. The invention can further employ feedback/feed-forward loop(s) to facilitate compensatory action in order to improve process control.