Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.

Abstract: One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.

Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.

Abstract: One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.

Abstract: A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.

Abstract: One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.

Abstract: One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

Abstract: A system and method is provided for applying a developer to a photoresist material wafer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. The developer plate is disposed in very close proximity with respect to the wafer, such that the developer is squeezed between the two plates thereby spreading evenly the developer over the wafer.

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract: One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.

Abstract: An edge bead removal system and method is provided that employs a nozzle for applying edge bead removal solvent to an edge bead of a photoresist material layer disposed on a wafer. The nozzle includes a liquid chamber that can be connected to a supply of edge bead removal and an air supply chamber that can be connected to a supply of air. The supply of air is isolated from the liquid supply chamber during application of the edge bead removal solvent and communicates via the air supply chamber to the liquid supply chamber after application of the edge bead removal solvent thus removing any droplets of edge bead removal solvent remaining in the nozzle tip. A system is also provided that includes an absorbent material that moves from a rest position, during application of the edge bead removal solvent, to an absorbing position that removes or catches any droplets of edge bead removal solvent remaining on the nozzle tip after application of the edge bead removal solvent is completed.

Abstract: One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.

Abstract: A system adapted to provide in-situ detection of closed area defects and a method for the same is provided. The system comprises a light source for directing light on to a wafer having a grating pattern etched thereon; a light detector for collecting the light reflected from the wafer; a processor operatively coupled to the light detector for converting the collected light into data associated with the grating pattern and determining the presence of the closed area defect; and a controller operatively coupled to the processor for determining whether the wafer requires additional processing to repair the closed area defect.

Abstract: The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract: A system and method are disclosed for providing in-situ monitoring of thin film thickness, such as by employing a non-destructive optical measurement technique. The monitored film thickness may be employed to help achieve a desired feature film thickness and uniformity across a surface of a substrate. By monitoring film thickness during semiconductor processing, for example, one or more process control parameters may be adjusted to help achieve a desired film thickness and/or uniformity thereof.

Abstract: The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.