Patents by Inventor Khoi A. Phan

Khoi A. Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7065737
    Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 7065427
    Abstract: A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Ramkumar Subramanian, Bharath Rangarajan, Khoi A. Phan
  • Patent number: 7064846
    Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) and/or standing wave expression during pattern line formation in an integrated circuit. Systems and methods are disclosed for retaining a target critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER and/or standing wave expression, wherein the shrink component is employed to heat a particular resist to the glass transition temperature of the resist to effectuate mitigation of LER and/or standing wave expression. Additionally, by heating the resist to its glass transition temperature, the systems and methods of the present invention effectively impede deviation from a desired target critical dimension.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gilles Amblard, Bhanwar Singh, Khoi A. Phan, Ramkumar Subramanian
  • Patent number: 7056646
    Abstract: Disclosed are immersion lithography methods involving using a base developer as an immersion lithography fluid. Consequently, it is unnecessary to contact a developer with an irradiated resist after the immersion lithography fluid is removed.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: June 6, 2006
    Assignee: Advanced Micro devices, Inc.
    Inventors: Gilles Amblard, Bhanwar Singh, Khoi A. Phan
  • Patent number: 7034930
    Abstract: A measuring system and method are provided for defect identification and location. The system an optical measurement device adapted to view a workpiece along an optical path, and an optical indicia device located in the optical path between the workpiece and the measurement device, which is adapted to provide location information to the system or a user. The location information can be used to correlate defect locations identified in a wafer before and after a process step, as well as between two different wafers. The optical indicia device may further allow the use of field comparison techniques in identifying and locating defects in a blank or unpatterned workpiece. The indicia device may comprise, for example, a transparent member having a grid or other optical indicia patterned thereon, allowing inspection of the workpiece with reference to the optical indicia pattern.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 25, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan
  • Patent number: 7001830
    Abstract: The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 21, 2006
    Assignee: Advanced Micro Devices, Inc
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6999254
    Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: February 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian
  • Patent number: 6972576
    Abstract: A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The system includes a reticle test system that is capable of applying a voltage to the probe points, measuring the resulting current, calculating the corresponding resistance of the test features, and determining the critical dimensions of the test features. The system is also capable of determining defects based on the resistance measurements. The critical dimension information and defect information can then be used to refine the processes used in the fabrication of subsequent reticles.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: December 6, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Khoi A. Phan, Cyrus E. Tabery, Bhanwar Singh
  • Patent number: 6972201
    Abstract: Architecture for monitoring a bottom anti-reflective coating (BARC) undercut and residual portions thereof during a development stage using scatterometry. The scatterometry system monitors for BARC undercut and residual BARC material, and if detected, controls the process to minimize such effects in subsequent wafers. If one or more of such effects has exceeded a predetermined limit, the wafer is rerouted for further processing, which can include rework, etch back of the affected layer, or rejection of the wafer, for example.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: December 6, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A. Phan
  • Patent number: 6954678
    Abstract: A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component provides potential solution(s) to a defect within the lithography process utilizing artificial intelligence technique(s) (e.g., Bayesian learning methods that perform analysis over alternative dependent structures and apply a score, Bayesian classifiers and other statistical classifiers, including decision tree learning methods, support vector machines, linear and non-linear regression and/or neural network).
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 6924157
    Abstract: One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: August 2, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
  • Patent number: 6915177
    Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 5, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 6844206
    Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: January 18, 2005
    Assignee: Advanced Micro Devices, LLP
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian
  • Patent number: 6818360
    Abstract: A system that monitors and controls a phase shift mask fabrication process is disclosed. Acoustic beams and/or beams of light are selectively directed at portions of the mask to scan the mask as it matriculates through the fabrication process. Portions of the beams that pass through and/or are reflected from the mask are collected and examined, such as in accordance with scatterometry based techniques, to determine, for example, whether cracks or other defects are forming on or within the mask, and/or whether features, such as apertures, are being formed as desired. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Controlling the mask fabrication process facilitates improved mask fabrication and resulting chip quality as compared to conventional systems.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 16, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
  • Patent number: 6809793
    Abstract: A system and method are disclosed which enable temperature of a substrate, such as mask or reticle, to be monitored and/or regulated. One or more temperature sensors are associated with the substrate to sense substrate temperature during exposure by an exposing source. The sensed temperature is used to control one or more process parameters of the exposure to help maintain the substrate at or below a desired temperature.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Ramkumar Subramanian, Bharath Rangarajan
  • Patent number: 6808591
    Abstract: A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Christopher F. Lyons, Steven C. Avanzino, Ramkumar Subramanian, Bhanwar Singh, Cyrus E. Tabery
  • Patent number: 6784446
    Abstract: One aspect of the present invention relates to a system and method for detecting defects on a reticle by inspecting latent images printed on a resist wafer by the reticle. The system includes a wafer having a printed photoresist layer formed thereon, a latent image inspection system connected to the wafer exposure system for examining the printed photoresist layer in order to determine whether a reticle employed to print the photoresist layer is defective, and a processor for receiving data from the inspection system in order to verify the presence of defects on the reticle. The method involves printing a first latent image, a second latent image, and a third latent image on a resist wafer using a reticle, and comparing the three latent images to one another to determine whether the reticle is defective. Comparison of the latent images may be facilitated by employing an optical system programmed to perform such comparisons.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 31, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
  • Patent number: 6771356
    Abstract: A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: August 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Bhanwar Singh, Steven C. Avanzino, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian, Cyrus E. Tabery
  • Patent number: 6762133
    Abstract: The present invention relates to systems and methods for mitigating pattern collapse in ultra-thin resist processing. In one embodiment, the present invention relates to etching extremely fine patterns into a hardmask immediately after developing an ultra-thin resist, wherein the resist is not dried.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan
  • Patent number: 6759179
    Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein, including special vapor prime and development operations.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: July 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Jeffrey Erhardt, Jerry Cheng, Richard J. Bartlett, Anthony P. Coniglio, Wolfram Grundke, Carol M. Bradway, Daniel E. Sutton, Martin Mazur