Patents by Inventor Khoi A. Phan

Khoi A. Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6320402
    Abstract: A system for inspecting semiconductor wafers of at least one lot of semiconductor wafers for proper integrated circuit fabrication includes multiple different inspection stations. Each of the different inspection stations inspects a respective integrated circuit fabrication feature of a semiconductor wafer. In addition, a semiconductor wafer robotic handling system, that is coupled to each of the inspection stations, transfers the semiconductor wafers between the inspection stations. Furthermore, a host server is coupled to the inspection stations and the semiconductor wafer robotic handling system. The host server controls the semiconductor wafer robotic handling system to transfer a predetermined one of the semiconductor wafers to a predetermined one of the inspection stations at a predetermined time.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: November 20, 2001
    Inventors: Khoi A. Phan, Bernard Matt, Nicholas R. Maccrae
  • Patent number: 6316277
    Abstract: There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: November 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Christopher F. Lyons, Khanh B. Nguyen, Jeff Schefske
  • Patent number: 6291135
    Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving contacting the semiconductor structure including the resist with a plasma comprising at least one inert gas selected from the group consisting of nitrogen, helium, neon, argon, krypton and xenon; exposing the semiconductor structure including the resist to actinic radiation having a wavelength of about 160 nm or less through a lithography mask; and developing the resist with a developer.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 18, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6270579
    Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: August 7, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
  • Publication number: 20010010229
    Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.
    Type: Application
    Filed: January 31, 2000
    Publication date: August 2, 2001
    Applicant: R. Subramanian
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo
  • Patent number: 6251570
    Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving the steps of exposing the semiconductor structure including the resist to acting radiation; contacting the semiconductor structure including the exposed resist with a solution comprising water and from about 0.01% to about 5% by weight of a surfactant; and developing the resist with a developer.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: June 26, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Ramkumar Subramanian, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6248175
    Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
  • Patent number: 6222936
    Abstract: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Gurjeet S. Bains, David A. Steele, Jonathan A. Orth, Ramkumar Subramanian
  • Patent number: 6190062
    Abstract: One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Bryan K. Choo, Sanjay K. Yedur
  • Patent number: 6171737
    Abstract: A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Shobhana R. Punjabi, Robert J. Chiu, Bhanwar Singh
  • Patent number: 6136514
    Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving the steps of exposing the semiconductor structure including the resist to actinic radiation; contacting the semiconductor structure including the exposed resist with a solution comprising water and from about 0.01% to about 5% by weight of a surfactant; and developing the resist with a developer.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: October 24, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Ramkumar Subramanian, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 5985497
    Abstract: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Gurjeet S. Bains, David A. Steele, Jonathan A. Orth, Ramkumar Subramanian