Patents by Inventor Kishore Kumar

Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DEVICE FOR DETECTING CHALLENGING BEHAVIORS IN PEOPLE WITH AUTISM
    Publication number: 20230363668
    Abstract: A method may include establishing a connection with a wearable device and at least one sensory module device disposed within an environment. The method may also include receiving, from the at least one sensory module device, a recording of an auditory input from a subject and physical movement of the subject in the environment. The method may further include receiving, from the wearable device, at least one physiological signal of the subject. In addition, the method may include detecting, via machine learning, presence of a challenging behavior of the subject based on the received record of the auditory input, the physical movement, and the at least one physiological signal of the subject. Further, the method may include transmitting a notification of the detected challenging behavior to an external device.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 16, 2023
    Inventors: Ahmad Yaser ALHADDAD, Ahmad Qadeib ALBAN, Malek AYESH, Abdulaziz Khalid AL-ALI, Kishor Kumar SADASIVUNI
  • MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS
    Publication number: 20230360705
    Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.
    Type: Application
    Filed: April 24, 2023
    Publication date: November 9, 2023
    Inventors: Huai-Yuan Tseng, Giovanni Maria Paolucci, Kishore Kumar Muchherla, James Fitzpatrick, Akira Goda
  • Selective read disturb sampling
    Patent number: 11810627
    Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Renato C. Padilla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • UFS based idle time garbage collection management
    Patent number: 11809729
    Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Jianmin Huang, Kishore Kumar Muchherla
  • Method, system, and medium for network and speed enhancement for distributing unified images via a computer network
    Patent number: 11803896
    Abstract: Methods for determining which image of a set of images to present in a search results page for a product are described. Components of a server system may receive a set of images for a set of items associated with a product. Components of the server system may perform image ranking to rank the set of images to identify a representative image of the set of images for the product, based on a user interaction metric of each image of the set of images. The components of the server system may then receive, from a user device, a search query that may be mapped to the product, and the component of the server system may transmit, to the user device, the search results page that includes at least one item of the set of items and the representative image based on the interaction metric of the representative image.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 31, 2023
    Assignee: eBay Inc.
    Inventors: Ramesh Periyathambi, Tomer Lancewicki, Kishore Kumar Mohan, Lakshimi Duraivenkatesh, Selcuk Kopru
  • SYSTEMS AND METHODS FOR PREDICTING PATIENT RESPONSES
    Publication number: 20230343117
    Abstract: Data processing systems for predicting one or more responses to a chemical substance based on biological images. At least some of the data processing systems include at least one processor configured to execute at least one artificial neural network trained to predict one or more responses to a chemical substance based on biological images. When the at least one processor is executing computer-executable instructions, the at least one processor is configured to carry out operations including processing spatially arranged image tile data through one or more data structures storing one or more portions of executable logic included in the artificial neural network to determine one or more responses of a patient to the chemical substance.
    Type: Application
    Filed: February 4, 2021
    Publication date: October 26, 2023
    Inventors: Vardaan Kishore Kumar, Qi Tang
  • Cache media management
    Patent number: 11797441
    Abstract: An exempt portion of a data cache of a memory sub-system is identified. The exempt portion includes a first set of data blocks comprising first data written by a host system to the data cache. A collected portion of the data cache of the memory sub-system is identified. The collected portion includes a second set of data blocks comprising second data written by the host system. A media management operation is performed on the collected portion of the data cache to relocate the second data to a storage area of the memory sub-system that is at a higher data density than the data cache, wherein the exempt portion of the data cache is exempt from the media management operation.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Sampath K. Ratnam, Kishore Kumar Muchherla, Peter Feeley
  • Detecting and preventing router-solicitation flood attacks
    Patent number: 11799903
    Abstract: An electronic device may receive a control packet from the second electronic device with a request for information about a router. Then, the electronic device may provide a response to the second electronic device with the information about the router, where the response is provided using unicast communication. Next, the electronic device may receive an optional acknowledgment from the second electronic device. Furthermore, the electronic device may store response information that indicates the response was provided to the second electronic device and the optional acknowledgment was received. When the electronic device receives one or more subsequent control packets from the second electronic device with the request for the information about the router, the electronic device may determine that there is malicious activity based at least in part on the response information and may perform a remedial action.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 24, 2023
    Assignee: ARRIS Enterprises LLC
    Inventors: Srinivasulu Venkataramaiah, Kiran Kumar Naraharisetty, Hemant Bhatnagar, Kishor Kumar Hosur Nagaraju
  • CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READS
    Publication number: 20230335201
    Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 19, 2023
    Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
  • DATA REORDERING AT A MEMORY SUBSYSTEM
    Publication number: 20230333770
    Abstract: A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
  • Power-on-time based data relocation
    Patent number: 11789862
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Renato C. Padilla, Sampath K. Ratnam, Saeed Sharifi Tehrani, Peter Feeley, Kevin R. Brandt
  • MACHINE-LEARNING SYSTEM AND METHOD FOR PREDICTING EVENT TAGS
    Publication number: 20230325468
    Abstract: Methods, computer systems, and apparatus, including computer programs encoded on computer storage media, for training a machine-learning model for predicting event tags. The system obtains event data that specifies, for each of a plurality of events, a respective set of text fields characterizing the respective event. The system generates, from the event data, encoded language features for the plurality of events. The system also obtains knowledge data that specifies information of the event data. The system generates, from the event data and the knowledge data, tag data specifying a respective tag for each of the plurality of events. The system generates, from the tag data and the encoded language features, a respective encoded feature vector for each of the plurality of events. The system combines the tag data with the encoded feature vectors to generate a plurality of training examples.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 12, 2023
    Inventors: Madhan Kumar Srinivasan, Kishore Kumar Gajula, Abdul Hammed Shaik, Ashish Pant
  • APPARATUS AND METHODS FOR THERMAL MANAGEMENT IN A MEMORY
    Publication number: 20230326527
    Abstract: Memories might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the memory to initiate an array operation on the array of memory cells, indicate an unavailability to initiate a next array operation, append a delay interval to an array access time of the array operation, and indicate an availability to initiate a next array operation in response to a completion of the delay interval. The delay interval might have a duration determined in response to an indication of temperature.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 12, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jeremy Binfet, Kishore Kumar Muchherla
  • MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES
    Publication number: 20230325273
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 12, 2023
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
  • Multi-tier threshold voltage offset bin calibration
    Patent number: 11783901
    Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo
  • Hydroalkylation of mononuclear aromatic hydrocarbons to mono cycloalkyl aromatic hydrocarbons
    Patent number: 11779914
    Abstract: An aspect of the present disclosure relates to a process for preparing a composite hydroalkylation catalyst including: (a) effecting impregnation of a hydrogenation metal on an inorganic oxide to form a metal impregnated inorganic oxide; (b) effecting calcination of the metal impregnated inorganic oxide to obtain a calcined metal impregnated inorganic oxide; (c) preparing a composite mixture comprising a molecular sieve, the calcined metal impregnated inorganic oxide and a binder; (d) preparing an extruded catalyst; and (e) effecting calcination of the extruded catalyst to obtain the composite hydroalkylation catalyst. The composite hydroalkylation catalyst prepared using this process affords dramatic improvement in conversion of mononuclear aromatic hydrocarbon and the yield of the hydroalkyled mononuclear aromatic hydrocarbon (e.g. CHB).
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: October 10, 2023
    Assignees: BHARAT PETROLEUM CORPORATION LIMITED, INDIAN INSTITUTE OF TECHNOLOGY DELHI
    Inventors: Ananth Kishore Kumar Sontyana, Nikita Sharma, Shivanand Mukund Pai, Bharat Lakshman Newalkar, Kamal Kishore Pant
  • Read count scaling factor for data integrity scan
    Patent number: 11782627
    Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
  • Performing a media management operation based on a sequence identifier for a block
    Patent number: 11782847
    Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Error Correction in a Memory Device having an Error Correction Code of a Predetermined Code Rate
    Publication number: 20230317195
    Abstract: An apparatus having memory cells, an error correction module with a predetermined code rate, a processing device configured to arrange data storage in the memory cells for improved capability in recovering from random bit errors in raw data retrieved from the memory cells. For example, user data and redundant data are stored in the memory cells. The redundant data is generated according to the predetermined code rate from not only the user data but also known data. The known data is not stored in the memory cells. As a result, the error correction module has increased capability in recovering from random bit errors in raw data retrieved from the memory cells. The increased capability can be used to extend the useful life of the memory cells and/or improve the reliability of retrieving error free data from the memory cells.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Mustafa N. Kaynak, Kishore Kumar Muchherla
  • Read error recovery
    Patent number: 11775181
    Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Harish Reddy Singidi, Ting Luo, Kishore Kumar Muchherla