Patents by Inventor Kishore Kumar

Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DATA REORDERING AT A MEMORY SUBSYSTEM
    Publication number: 20240176532
    Abstract: A set of data items programmed to a first region of a memory subsystem is identified. The set of data items is programmed to the first region according to an initial sequence. A determination is made of whether the initial sequence corresponds to a target sequence associated with accessing the set of data items. Responsive to a determination that the initial sequence does not correspond to the target sequence, the set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 30, 2024
    Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
  • Selective partitioning of sets of pages programmed to memory device
    Patent number: 11995326
    Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Mastafa N. Kaynak, Devin M. Batutis, Xiangang Luo
  • Multi-layer code rate architecture for special event protection with reduced performance penalty
    Patent number: 11994947
    Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Mustafa N. Kaynak, Akira Goda, Sivagnanam Parthasarathy, Jonathan Scott Parry
  • One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques
    Patent number: 11990186
    Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Phong Sy Nguyen, James Fitzpatrick, Kishore Kumar Muchherla
  • MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM
    Publication number: 20240160359
    Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo’ Righetti, Ugo Russo
  • MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB
    Publication number: 20240161838
    Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: Nicola Ciocchini, Animesh Roy Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei, Niccolo’ Righetti, Jonathan S. Parry, Ugo Russo
  • Adjustment of code rate as function of memory endurance state metric
    Patent number: 11983067
    Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 14, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Niccolo′ Righetti, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, James Fitzpatrick, Ugo Russo
  • Workload-based scan optimization
    Patent number: 11977778
    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
  • Erase cycle healing using a high voltage pulse
    Patent number: 11978514
    Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe
  • Method of producing thin enzyme-based sensing layers on planar sensors
    Patent number: 11969246
    Abstract: A sensor implanted in tissues and including a sensing layer is fabricated by mixing the signal transduction enzyme with non-reactive components including buffer salts and fillers, and spin coating the enzyme onto a substrate. The signal transduction enzyme is crosslinked by introducing the coated substrate in a vacuum chamber. In the chamber, a crosslinker evaporates and is deposited onto the enzyme, therefore crosslinking the enzyme.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 30, 2024
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Samson Chen, Axel Scherer, Dvin I. Adalian, Peter Petillo, Muhammad Musab Jilani, Xiomara L. Madero, Deepan Kishore Kumar
  • USING DUPLICATE DATA FOR IMPROVING ERROR CORRECTION CAPABILITY
    Publication number: 20240134571
    Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Patrick R. Khayat, Sundararajan Sankaranarayanan, Jeremy Binfet, Akira Goda
  • Voltage bin calibration based on a voltage distribution reference voltage
    Patent number: 11966616
    Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
  • MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
    Publication number: 20240126690
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • Memory device programming technique for increased bits per cell
    Patent number: 11960722
    Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
  • TEMPORARY PARITY BUFFER ALLOCATION FOR ZONES IN A PARITY GROUP
    Publication number: 20240118971
    Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 11, 2024
    Inventors: Kishore Kumar Muchherla, David Scott Ebsen, Akira Goda, Jonathan S. Parry, Vivek Shivhare, Suresh Rajgopal
  • BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES
    Publication number: 20240111445
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • WEB-BASED WORKLOAD MANAGEMENT WITH ASYNCHRONOUS WORKLOAD EXECUTION AND REAL-TIME USER FEEDBACK
    Publication number: 20240111605
    Abstract: A workload management system includes a workload management tool configured to generate a workload context associated with a workload generated based on interactions of a user with workload initiation controls presented within a user interface (UI) of a client application. The workload context includes instructions for transmitting the workload context from a main browser session to a first background browser session; executing the workload within the first background session; and for configuring a first event handler within the main session to wait for a first event generated within the first background session in association with execution of the workload and, in response to receipt of the first event, transmit the client application an instruction to present workload status information in the user interface.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Andres MARTINEZ ANDRADE, Kishore Kumar PENUGONDA, Yanli TONG, Ganapathi SADASIVAM
  • PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTEM BASED ON AN UNSUCCESSFUL ERROR CORRECTION OPERATION
    Publication number: 20240103749
    Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Performing a program operation based on a high voltage pulse to securely erase data
    Patent number: 11942160
    Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • Collimator for a physical vapor deposition (PVD) chamber
    Patent number: D1026054
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 7, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Martin Lee Riker, Keith A. Miller, Luke Vianney Varkey, Xiangjin Xie, Kishor Kumar Kalathiparambil