Patents by Inventor Kishore Kumar

Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941285
    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Giuseppina Puzzilli, Saeed Sharifi Tehrani
  • Publication number: 20240092578
    Abstract: A system and method for transferring items in a storage facility are provided. The storage facility includes a storage system that includes bins, a control server, and a sensing system. A pick-put operation on an inventory item is performed by picking the inventory item from a robotic apparatus by an operator and storing the inventory item in a corresponding bin of the storage system. The control server receives sensor signals when the sensing system automatically senses a pick-up of the inventory item from the robotic apparatus and placement of the inventory item in the corresponding bin of the storage system. The reception of the sensor signals by the control server indicates execution of the pick-put operation. Thus, a need for the operator to manually scan the inventory item during the pick-up or press any buttons on the storage system to indicate completion of the pick-put operation is eliminated.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 21, 2024
    Applicant: Grey Orange Inc.
    Inventors: Vivek AGGARWAL, Mohit AGRAWAL, Kishore Kumar LUTHRA, Shivam NAGAR
  • Patent number: 11934689
    Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Gianni Stephen Alsasua, Renato Padilla, Jr., Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish Reddy Singidi
  • Patent number: 11934266
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
  • Patent number: 11934686
    Abstract: A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
  • Publication number: 20240087651
    Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
  • Publication number: 20240086282
    Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Mustafa N. Kaynak, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, James Fitzpatrick, Mark A. Helm
  • Patent number: 11928353
    Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Patent number: 11928347
    Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mustafa N Kaynak, Peter Feeley, Sampath K Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D Schuh, Jiangang Wu
  • Publication number: 20240079131
    Abstract: A system for facilitating performing a therapeutic activity at a predetermined treatment site in a patient is provided. The system comprises an elongated miniature device extending along a longitudinal axis spanning between a distal cutting end formed with a sharp cutting portion, and a blunt proximal abutting end. The elongated body comprises a substantially non-convex bottom surface extending substantially between the cutting end and the abutting end. The system further comprises a driving device configured to generate a varying magnetic field to remotely control motion of the miniature device.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 7, 2024
    Applicant: BIONAUT LABS LTD.
    Inventors: Kishore Kumar KONDABATNI, Michael KARDOSH, SueHyun CHO, Florent CROS, Michael SHPIGELMACHER, Alex KISELYOV
  • Patent number: 11923021
    Abstract: A memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. A temperature level associated with the memory unit is determined. Based on the time after program and the temperature level, a set of read offset values to apply in executing the read operation is determined. The read operation is executed using the set of read offset values.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Larry J. Koudele
  • Patent number: 11922029
    Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Ugo Russo
  • Publication number: 20240071522
    Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Nicola Ciocchini, Animesh R. Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
  • Publication number: 20240069765
    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana K. Vakati, Jeffrey S. McNeil
  • Publication number: 20240071435
    Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.
    Type: Application
    Filed: May 17, 2023
    Publication date: February 29, 2024
    Inventors: Phong Sy Nguyen, Patrick R. Khayat, Jeffrey S. McNeil, Dung Viet Nguyen, Kishore Kumar Muchherla, James Fitzpatrick
  • Publication number: 20240071510
    Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda, Jeffrey S. McNeil, Umberto Siciliani, Daniel J. Hubbard, Walter Di Francesco, Michele Incarnati
  • Publication number: 20240070084
    Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A flush command is received from a host system. A cached data item is retrieved from a volatile memory. The cached data item and at least a subset of the valid data stored at the victim MU are written to a target MU.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Akira Goda
  • Publication number: 20240070023
    Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Kishore Kumar Muchherla, Niccolo' Righetti, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, James Fitzpatrick, Ugo Russo
  • Publication number: 20240070588
    Abstract: Aspects of the present disclosure provide systems, methods, and computer-readable storage media that support application portfolio management. Input data may be received that is associated with a set of applications. The input data may indicate, for each application of the set of applications, a name of the application and a description of the application. For an application of the set of applications, a functional score, a cost, and a technical score may be determined based on the name of the application, the description of the application, or a combination thereof. A disposition recommendation for the application may be determined based on the functional score, the cost, and the technical score. In some implementation, an indication of the disposition recommendation of the application may be output via a graphical user interface.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sandeep Bharihoke, Kishore Kumar Sampath, Akshaya Purushothama Kadidal, Logesh Subramani, Barun Prakash Nanda, Shiv Chhabra, Ganesan Ramachandran, Andrew Lanktree, Neeraj Arora
  • Patent number: 11914490
    Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Jianmin Huang, Xiangang Luo, Ashutosh Malshe